similar to: [LLVMdev] ScheduleDAGInstrs.cpp

Hello again, Sorry -- I think I found the problem somewhere else. I was a bit confused and missed the fact that adjustChainDeps() is called a few lines down and does just what I wanted :-) I would like to instead ask another question: Why is I->isCtrl() used in code like // Iterate over chain dependencies only. for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E =

Hi, Thank you for the reply. >It looks to me like we can choose any subset of edges here and be correct. We're basically trying to prune/pinch the DAG edges here. They can easily blow up with AA sched. I would guess that isCtrl() edges are good ones to bypass because they could be a low-latecy edges, whereas true data dependencies from a load are expected to be >higher latency, so they

Hi, I have revisited the issue in buildSchedGraph() I talked about previously, and attached a few patches. The first tries to fix the issue, and the other two try to illustrate associated issues, emerged from applying it. Is it OK to commit the first patch? [PATCH] Bugfix for missed dependency from store to load in buildSchedGraph(). Bugfix for missed dependency from store to load in

Hi, I write again regarding buildSchedGraph(), as I am still not happy about things there. I have found at least two examples which do not work out: 1) SU(2) Store "Value A" SU(1) Store "Value A" SU(0) Load "Value A" If MIsNeedChainEdge() returns false for SU(0) and SU(1), SU(0) is inserted into RejectedMemNodes and removed from its MemUses SU list, as this

Dear R developers, sessionInfo() below Please have a look at the following two versions of the same function: 1. Intended behavior: > Su1 = function(u=100, l=u, mu=0.53, sigma2=4.3^2) + { + print(c(u, l, mu)) # here, l is set to u?s value + u = u/sqrt(sigma2) + l = l/sqrt(sigma2) + mu = mu/sqrt(sigma2) + print(c(u, l, mu)) + } > > Su1() [1] 100.00 100.00 0.53 [1]

On Nov 9, 2011, at 2:12 PM, Chris Lattner wrote: > On Nov 9, 2011, at 1:08 PM, Jim Grosbach wrote: >>> On Nov 9, 2011, at 10:49 AM, Jim Grosbach wrote: >>>>> >>>>> It's not good, but people do it. Also constructing enums via & and | etc. It'd be nice to be able to get the name of whatever it is that the code generator actually produced :)

Another way to avoid the problem is to not redefine variables that are arguments. E.g., > Su3 <- function(u=100, l=u, mu=0.53, sigma2=4.3^2, verbose) { if (verbose) { print(c(u, l, mu)) } uNormalized <- u/sqrt(sigma2) lNormalized <- l/sqrt(sigma2) muNormalized <- mu/sqrt(sigma2) c(uNormalized, lNormalized, muNormalized) } > Su3(verbose=TRUE)

Hello, One way of preventing that is to use ?force. Just put force(l) right after the commented out print and before you change 'u'. Hope this helps, Rui Barradas Citando Matthias Gondan <matthias-gondan at gmx.de>: > Dear R developers, > > sessionInfo() below > > Please have a look at the following two versions of the same function: > > 1. Intended

Mathias, If it's any comfort, I appreciated the example; 'expected' behaviour maybe, but a very nice example for staff/student training! S Ellison > -----Original Message----- > From: R-help [mailto:r-help-bounces at r-project.org] On Behalf Of Matthias > Gondan > Sent: 02 September 2017 18:22 > To: r-help at r-project.org > Subject: [R] Strange lazy evaluation of

Dear Bill, All makes perfect sense (including the late evaluation). I actually discovered the problem by looking at old code which used your proposed solution. Still I find it strange (and, hnestly, I don?t like R?s behavior in this respect), and I am wondering why u is not being copied to L just before u is assigned a new value. Of course, this would require the R interpreter to track all these

Hi, I have committed the patch now (svn id 228686). Regarding the commenting you requested, I attach a patch. Feel free to make changes. I found it difficult to explain what the code does in isolated places, and thus kept my commenting quite short. This makes me feel like the code needs a bit of refactorization to make it more simple and understandable. Looking at the possibility of

Hi, all, Does anybody got the most general expression of a unitary matrix? I found one in the book, four entries of the matrix are: (cos\theta) exp(j\alpha); -(sin\theta)exp(j(\alpha-\Omega)); (sin\theta)exp(j(\beta+\Omega)); (cos\theta) exp(j\beta); where "j" is for complex. However, since for any two unitary matrices, their product should also be a unitary matrix. When I

Hi, (This only concerns MISNeedChainEdge(), and is separate from D8705) I found out that the MIScheduler (pre-ra) could not handle a simple test case (test/CodeGen/SystemZ/alias-01.ll), with 16 independent load / add / stores. The buildSchedGraph() put too many edges between memory accesses, because 1) There was no implementation of areMemAccessesTriviallyDisjoint() for SystemZ. 2) Type

> On Jan 19, 2012, at 5:31 AM, Jonas Paulsson wrote: > LLVM would have to be extended with an RegClass/register-attribute 'spillable' > > > What exactly are you proposing? Why can't you do what the PowerPC and Hexagon targets do? Yes, I can move a CR to a GPR and save it to the stack, but due to a very irregular register file this is about 10 times more expensive

OK, finally found it. The AliasChain in ScheduleDAGInstrs::buildSchedGraph is not acting as a chain for loads and stores (the head of the chain is not being updated as they are encountered, so dependencies aren't being added solely on the basis of may-aliasing in some cases). Will test a patch. On Fri, 2012-09-21 at 13:04 -0500, William J. Schmidt wrote: > On Fri, 2012-09-21 at 11:34

On Jan 19, 2012, at 5:31 AM, Jonas Paulsson wrote: > LLVM would have to be extended with an RegClass/register-attribute 'spillable' What exactly are you proposing? Why can't you do what the PowerPC and Hexagon targets do? Spill-free register allocation sounds great, why not do it for all register classes? > , and a register allocator would have to implement register pairing.

On Jan 20, 2012, at 6:40 AM, Jonas Paulsson wrote: > > What exactly are you proposing? Why can't you do what the PowerPC and Hexagon targets do? > > Yes, I can move a CR to a GPR and save it to the stack, but due to a very irregular register file this is about 10 times more expensive than saving/restoring an ordinary register. These registers should basically never > have to

Hello everybody! I have an Asterisk 1.2.12.1 server with SIP as the VoIP protocol. What I want to do: I want to talk to the "outside world" via MGCP. I suppose I must set an MGCP peer to route outgoing calls. So, I must set the endpoint syntax of the Asterisk server (Asterisk will act as an MGCP gateway and will talk with an MGCP Gatekeeper) and with other MGCP gateways via

Unfortuantely we don't know if a particular load is a real 2d image (as would be a cube face or 2d array element), or a layer of a 3d image. Since we pass in the TIC reference, the instruction's type has to match what's in the TIC (experimentally). In order to properly support bindless images, this also can't be done by looking at the current bindings and generating appropriate

Hi, My target has special requirements during register allocation - there is both a need to handle register pairing and to never spill a flag result reg-class (which might happen at -O0 for no obvious reason). Since neither of these issues seems to be supported, I have tried to pre-allocate these registers in the preRA pass. This has resulted in "using undefined physical register"