similar to: [LLVMdev] TSFlags in AsmBackend

Hello all, I wan to ask, what is exactly the purpose of TSFlags and can it be used for the condition handling in instructions? How can I implement the conditions in the instruction when I don't have access to the Status Register? Best regards, ES -------------- next part -------------- An HTML attachment was scrubbed... URL:

Many thanks for your prompt reply. I mean, imagine you have 3 bits for condition flags in your instruction (e.g. overflow, zero, carry set, ...) for conditional executions AND there is no direct access to the Status Register, is it even possible to implement such scenario? On Fri, Jul 10, 2015 at 4:54 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 7/10/2015 9:32

On 7/10/2015 10:23 AM, Sky Flyer wrote: > Many thanks for your prompt reply. > > I mean, imagine you have 3 bits for condition flags in your instruction > (e.g. overflow, zero, carry set, ...) for conditional executions AND > there is no direct access to the Status Register, is it even possible to > implement such scenario? > There doesn't have to be any explicit status

Jakob, I think this exactly what's happening. I debugged the resolveReferences for the ADD down into the resolve of TSFlags. It calls VarInit::getFieldInit for the "Val" field of "foo". The code is: Init *VarInit::getFieldInit(Record &R, const RecordVal *RV, const std::string &FieldName) const { if (isa<RecordRecTy>(getType()))

Hi Krzystof, regarding your first solution (creating separate instruction), is it possible to somehow have cascading defm? for example, let's suppose aaa is a 3-bit condition a, and bb is a 2-bit condition b, all in one instruction, instead of having one multiclass with 2^5 conditions, is it possible to write 2^3 "a" conditions, and 2^2 "b" conditions, and the rest taken

I think we can get rid of the TSFlagsFields and TSFlagsShifts hack in the InstrInfo TableGen class now. This seems to work just fine: class Instruction { bits<32> TSFlags; } class Domain<bits<2> val> { bits<2> Value = val; } def GenericDomain : Domain<0>; def SSEPackedInt : Domain<1>; def SSEPackedSingle : Domain<2>; def SSEPackedDouble :

It seems like this code should work with Tablegen, but it generates the error: "error:Invalid TSFlags bit in ADD" Here's the code: =================================== include "llvm/Target/Target.td" def MyInstrInfo : InstrInfo; def MyTarget : Target { // Information about the instructions... let InstructionSet = MyInstrInfo; } def r1 :

Hi all. There are two steps in LTO codegen so the problem is how to pass ABI info into LTO code generator. The easier way is pass -target-abi via option to LTO codegen, but there is linking issue when linking two bitcodes generated by different -mabi option. (see https://reviews.llvm.org/D71387#1792169) Usually the ABI info for a file is derived from target triple, mcpu or -mabi, but in RISC-V,

David Blaikie <dblaikie at gmail.com> 於 2020年1月6日 週一 下午2:23寫道： > If this is something that can vary per file in a compilation and resolve > correctly when one object file is built with one ABI and another object > file is built with a different ABI (that seems to be antithetical to the > concept of "ABI" Though) - then it should be a subtarget feature. > > ABI is

Hello, I'm trying to write assembler code writer, and of course, have new questions. I'd like the structure my implementation like this: if (/*binary instruction*/) { // print destination O << " = "; // print first operand O << opcode; // print second operand. } if (/* unary instruction */ ) { .... } if (/*control instruction*/) { ....

On Mon, 7 Jun 2004, Vladimir Prus wrote: > > Hello, > I'm trying to write assembler code writer, and of course, have new questions. > I'd like the structure my implementation like this: > if (/*binary instruction*/) { > if (/* unary instruction */ ) { > if (/*control instruction*/) { Okay, that should be no problem. > The question is how to write those

On Jan 31, 2013, at 9:27 AM, Sean Silva <silvas at purdue.edu> wrote: > An extra call to resolveReferences after setting the value in the > `let` does fix this, but I'm not sure that it is the right fix. The > attached hackish patch seems to fix up a reduced version of the test > case you gave here (I haven't run a full battery of tests on it, so it > might cause

An extra call to resolveReferences after setting the value in the `let` does fix this, but I'm not sure that it is the right fix. The attached hackish patch seems to fix up a reduced version of the test case you gave here (I haven't run a full battery of tests on it, so it might cause other failures). Jakob, any idea about what the "right" fix is here? -- Sean Silva

When I query for installed package on the system, I get following result: # yum list installed openssl Loaded plugins: fastestmirror, tsflags, verify, versionlock Loading mirror speeds from cached hostfile Installed Packages openssl.x86_64 1.0.1e-16.el6_5.4 @updates/$releasever When I try to install already installed package (just playing with yum), I get following result: # yum install

Thank You. My add instruction has TA as follows: def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, TA; so i defined; bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used

Hello, I'm working on an LLVM backend for an experimental microprocessor. Work is going on nicely, and I've until now found the answer to all my questions directly in the LLVM source code, or in the documentation. However, I'm having problems with the AsmBackend class and the handling of fixups. The processor I'm working with has a single conditional branch instruction, JCC,

Hello, I am trying to emit binary for my implemented vector instructions. Although yet i havent done any change or addition in MC framework, For vector load instruction there are no error coming. But for vector add instruction is something like this; > %R_0_REG2048b_1<def> = P_256B_VADD %R_0_REG2048b_1<kill>, %R_0_REG2048b_0<kill> I am getting the following error: Unknown

You are right. But when i defined my instruction as follows: def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V; I get opcode conflicts? Then what to do? On Tue, Sep 5, 2017 at 3:51 AM,

Sorry to ask but what does it mean to put both? On Tue, Sep 5, 2017 at 4:01 AM, Craig Topper <craig.topper at gmail.com> wrote: > Leave TA. Put both. > > ~Craig > > On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> You are right. But when i defined my instruction as follows: >> def P_256B_VADD : I<0xE1,

I was getting same error when i keep both EVEX/EVEX_4V and TA. So, i restored my original instructions and for that i have to include bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp then used this condition; if(HasTA) ++SrcRegNum; in order to emit binary correctly. Is it right? On Tue, Sep 5, 2017 at 5:45 AM, Craig Topper <craig.topper at gmail.com> wrote: >