similar to: [LLVMdev] Stange behavior in fp arithmetics on x86 (bug possibly)

On Oct 7, 2014, at 2:26 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Dmitry, > > On 7 October 2014 10:50, Dmitry Borisenkov <d.borisenkov at samsung.com> wrote: >> fpfail.s:26: Error: invalid instruction suffix for `ret' >> >> I downloaded Intel manual and haven’t found any mention of retl instruction, > > "retl" is the

That what I actually did now, locally in the code. But I still see the " movabsq" .text .align 8, 0x90 .LCPI0_0: .quad 4606281698874543309 # double 0.9 .LCPI0_1: .quad 4631147119616759172 # double 42.2794408 .LCPI0_2: .long 1065353216 # float 1 .zero 4 ... movabsq $.LCPI0_1, %rax # encoding: [0x48,0xb8,A,A,A,A,A,A,A,A]

Looks like pinsr is not being generated on llvm-x86_64-ubuntu... jabbey at davinci:~$ /home/jabbey/src/osuosl/buildbot/sandbox/llvm-x86_64-ubuntu/llvm-x86_64-ubuntu/llvm/Debug+Asserts/bin/llc < /home/jabbey/src/osuosl/buildbot/sandbox/llvm-x86_64-ubuntu/llvm-x86_64-ubuntu/llvm/test/CodeGen/X86/mmx-pinsrw.ll -mtriple=x86_64-linux -mattr=+mmx,+sse2 produces: .file "<stdin>"

Hi Rafael, Yes, merging gv prevents linker to do garbage collection. Should it be implemented as a peephole pass? If we do it too early, the distance between GVs are not fixed yet. PS: Below is the GCC output with "extern" hidden: ldr r2, .L2 stmfd sp!, {r3, lr} .save {r3, lr} .LPIC0: add r0, pc, r2 bl _Z4initPv(PLT) ldr r1, .L2+4 .LPIC1: add r0, pc, r1 bl _Z4initPv(PLT) ldr

Thank You, It means vmovdqa64 zmm22, zmmword ptr [rip + .LCPI0_0] # zmm22 = [8,9,10,11,12,13,14,15] zmm22 will contain 64 bit constant values which are indexes here zmm22=8, 9, 10, 11, 12,13,14,15. not the values loaded from these locations. and zmm2 contains constant 4000. so, vpmuludq zmm14, zmm10, zmm2 ; will multiply the indexes values with 4000, as for array b the stride is 4000. zmm14=

Hi Adam, John is right, the TCE stuff would be useful for you. Our compiler targets a processor template that the designer can populate pretty freely. The compiler then reads the architecture description and creates an LLVM backend on the fly. Please don't hesitate to get in touch with us if you have questions. -- Pertti

On Thu, 04 Jun 2009 22:55:04 +0200, Pertti Kellomäki <pertti.kellomaki at tut.fi> wrote: > Hi Adam, > > John is right, the TCE stuff would be useful for you. Our > compiler targets a processor template that the designer can > populate pretty freely. The compiler then reads the architecture > description and creates an LLVM backend on the fly. > > Please don't

This is a question about optimizing the code generation in a (new) Z80 backend: The CPU has a couple of 8 bit physical registers, e.g. H, L, D and E, which are overlaid in 16 bit register pairs named HL and DE. It has also a native instruction to load a 16 bit immediate value into a 16 bit register pair (HL or DE), e.g.: LD HL,<imm16> Now when having a sequence of loading two 16

Hello gyus, I am working on a project, where we are trying to create a development environment for new ASIP processor design. Part of this project is a compiler generator, where we would like to generate C compiler from some instruction description. To keep it short, let's say, that in each instruction's semantics is described by some C code. What I would like to do is to compile this

Hello. I have been trying to check, how llvm works on Solaris recently. First I have tested lli, whitch seems to execute the bytecode generated on Linux without any problems. However, llc has failed to generate valid SPARC assembler code even on the helloworld example. Here is the generated code: sakharov at trillian:~$ cat ./test.s .text .align 16 .globl main

Hello, I'd like to write some unit tests which verifies SELECT_CC and BR_CC lowering for ARM target, but I'm almost completely unfamiliar with llvm/Target. How can I get this nodes in DAG? Thanks. -- Kind regards, Dmitry Borisenkov -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi all, I have this problem with lattice that xyplot() won't draw some of my axis labels if the type (i.e. the relation argument) of scales is set as free. For example, in the plot below, I would want it to also show: 1. the labels E1,...E6 below the 10th panel (i.e. 3rd row, 2 col)....just as it is now done below the 12th panel.... 2. as well as the labels (2,4,6,8) on the top of panels 1

Hello, Depending on how I extract integer lanes from an x86_64 xmm register, the backend may spill that register in order to load scalars. The effect was observed on two targets: corei7-avx and btver1 (I haven't checked other targets). Here's a test case with spilling/no-spilling code put on conditional compile: #if __SSE4_1__ != 0 #include <smmintrin.h> #else #include

On Apr 18, 2007, at 2:07 PM, Evan Cheng wrote: > > On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote: > >> I noticed that the TableGen code emitter generator assumes that >> the instruction fields are declared in the instruction format in >> the same order that operands are defined. This seems like a bad >> dependence to me, and that TableGen should match

Environment: CentOS 4.2 (RHES4 clone) Ruby 1.8.4 Rails 1.0 I am having a small difficulty with case sensitive matching in some ruby code: f_nam_re = Regexp.new(f_nam_re_s,"x") produces these test results: The passed regexp: ^QPCCCMR[[:digit:]]$ The regexp used is: /^QPCCCMR[[:digit:]]$/i $= is false qpcccmr1 matches QPCCCMR1 matches QPCCMMR1 does not match qpCCCMR1 matches QPCCCMRC

Hi! I''m developing an application with Rails 1.2.6 and I''ve facing a weird problem. In a form, I''m using link_to_function that is aggregating a :partial, the code is as follows: <table> <thead> <tr> <th>Marca</th> <th>Porcentaje</th> <th>Objetivo Mensual</th>

Hi I am having strange problem using samba share using Linux file managers like nautilus and konquers. I can successfully mount samba share using smb://mnt/c but every time it asks for password. When I click on one folder and come back it again asks for password and that is very annoying. Pls help me Komal

Hi all, I have a SPA 1001 with DTMF set to auto. A sip.conf peer with codec alaw, ulaw, g729. I have dtmf=inband as this peer was only supporting alaw/ulaw. They just add g729, it's a GW to landline phones. A call passing through this peer give me "WARNING Inband not supported with g729, use RFC2833 instead". The call is connecting and DTMF is working. Now I'm coming back

Greetings, CentOS. After up2dating one of the corporate mail servers to CentOS 4.4 (was CentOS 4.2) and upgrading kernel to kernel-smp-2.6.9-42.0.3.EL, the following kernel messages started to appear in syslog: [root at gamma ~]# dmesg ........... ...CUT..... ........... lockd: unexpected unlock status: 1 lockd: unexpected unlock status: 1 lockd: unexpected unlock status: 1 lockd: unexpected

I posted a rather lengthy message a few weeks ago. Andrew B and Jerry both responded with indications of furthers investigation required....i was wondering if anyone found anything strange because I've had to go back to 2.2.5 to support those clients and with a bit of fear of potential strange behaviour in my XP clients. Don't wish to be a pest, but you guys have done so much for our