similar to: [LLVMdev] Physical register definition removed by MachineCSE

Hi Jim. I'm doing custom lowering but here I have a very basic issue and the situation is like this - [Original Op] Mul Dest, Src1, Src2 [Expanded from EmitInstrWithCustomInserter] Step1 Dest, Src1, Src2    <=== BuildMI(..., Step1, Dest).addReg(Src1).addReg(Src2) Step2 Dest, Src1, Src2    <=== BuildMI(..., Step2, Dest).addReg(Src1).addReg(Src2) Step3 Dest, Src2, Src1    <===

Hi Girish, Sorry, but I'm afraid I don't understand your question. Can you elaborate a bit? -Jim On Dec 19, 2011, at 9:12 PM, girish gulawani wrote: > > Hello Jim. > Just out of curiosity, won't such mechanism work via the patterns from instructions defs? > > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: Johannes

Hello Jim. Just out of curiosity, won't such mechanism work via the patterns from instructions defs? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> >Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Monday, 19 December 2011 10:33 PM

Ah, OK. I think I understand much better now. Thanks! You shouldn't need bundles for that sort of thing. A custom lowering or a fancy pattern should be sufficient, depending on the details of how your target is defined. For patterns, looks at the various targets use of the Pat<>, Pattern<>, ComplexPattern<> and related classes in the .td files. For examples of custom

Hi, Jim. In my case the target (Tilera) doesn't have a full 32-bit mult operation and to do so it has to accumulate results from three 16-bit mults, by retaining operands and the result across in the same registers. However the ISel DAG thinks its a CSE case. Please note this is not a MAdd/MSub triad. How could I do this by defining such a sequence or the pattern in the .def file itself for

Hi Johannes, You may be interested in the (very) recently added explicit instruction bundle support. For an example of their usage, have a look at the ARM backend's IT-block (Thumb2 predication support) pass, which uses them to tie instructions together. -Jim On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > Hello, > > I'm writing for a backend and have a complicated

Hello, I'm writing for a backend and have a complicated instruction bundle (3 instructions) that has to be executed like a single block (meaning: if the first instruction is executed, all three have to be executed to obtain the result, though not necessarily without other instructions in between). Unfortunately, MachineCSE gets in the way sometimes and rips it apart. Is there a way to

Hi, On 03/30/2016 11:38 AM, Matt Arsenault wrote: > >> On Mar 30, 2016, at 11:35, Mikael Holmén <mikael.holmen at ericsson.com >> <mailto:mikael.holmen at ericsson.com>> wrote: >> >> i16 (divm16_pseudo …) >> >> stuff? >> >> I've tried >> (i16, i16 (divm16_pseudo i16:$src1, i16:$src2) >> and >> ((i16, i16)

Hi, I have a problem regarding sub-register definitions and LiveIntervals on our target. When a subregister is defined, other parts of the register are always left untouched - they are neither read or def:ed. It however seems that Codegen treats subregister definitions as somehow clobbering the whole register. The SSA-code looks like this after isel: (Reg0 and Reg1 are 16bit registers. Reg2,

Hi, On 08/07/2015 10:30 PM, Nick Lewycky wrote: [...] > Depends. What is the exact declaration of format_long? > > > In the input .ll file it is: > > ; Function Attrs: minsize optsize > define internal i16 @format_long(i16* %res.8.par, i16 %base.9.par, > i32 %x.10.par) #3 { > > which is later changed somewhere in opt to: > > ;

If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. Evan On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > Hello, > > I'm writing for a backend and have a complicated instruction bundle (3 > instructions) that has to be executed like a single block (meaning: if > the first instruction

On 08/07/2015 01:53 PM, Caldarale, Charles R wrote: >> From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] >> On Behalf Of Mikael Holmén via llvm-dev >> Subject: [llvm-dev] load instruction erroneously removed by GVN > >> But between the load and the alloca there is also >> call fastcc void @format_long(i16* %_tmp30, i16 10, i32 10), !dbg !22 >>

On 03/30/2016 11:51 AM, Matt Arsenault wrote: > >> On Mar 30, 2016, at 11:43, Mikael Holmén <mikael.holmen at ericsson.com> wrote: >> >> Hi, >> >> On 03/30/2016 11:38 AM, Matt Arsenault wrote: >>> >>>> On Mar 30, 2016, at 11:35, Mikael Holmén <mikael.holmen at ericsson.com >>>> <mailto:mikael.holmen at

Hi Evan. The hasSideEffects method I believe operates only on Inline Assembly (IA) blocks. What if such a sequence is not part of IA? Thanks. Girish. If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. > >Evan > >On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > >> Hello, >>

> On Mar 30, 2016, at 11:43, Mikael Holmén <mikael.holmen at ericsson.com> wrote: > > Hi, > > On 03/30/2016 11:38 AM, Matt Arsenault wrote: >> >>> On Mar 30, 2016, at 11:35, Mikael Holmén <mikael.holmen at ericsson.com >>> <mailto:mikael.holmen at ericsson.com>> wrote: >>> >>> i16 (divm16_pseudo …) >>>

On 07/15/2019 04:01 AM, Mikael Holmén via llvm-dev wrote: > Hi, > > Same thing for me, as I described here: > > http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20190708/279184.html > > I think the problem is that the patch assumes that if sys/inotify.h > exists, then IN_EXCL_UNLINK is defined in it. > > But I think that there are old versions of inotify.h

Looks like I can't access git, documentation, bugs... I'm not sure if this email will actually go through. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20171009/e63b709a/attachment.html>

Hi, A few days ago I stumbled upon a problem where SpeculativeExecution changed the order of a load and a store to the same address. I wrote https://bugs.llvm.org//show_bug.cgi?id=32964 about it but no response there so far. In the input we have store i8 0, i8* @i %.pre = load i8, i8* @i and then in the output the load is moved so it's before the store which clearly makes it

Hi, I'm trying to run the benchmark suite: http://llvm.org/docs/TestingGuide.html#test-suite-quickstart I'm doing it the lnt way, as described at: http://llvm.org/docs/lnt/quickstart.html I don't know what to expect but the results seems to be quite noisy and unstable. E.g I've done two runs on two different commits that only differ by a space in CODE_OWNERS.txt on my 12

Hi, I'm having a problem with GVN removing a load instruction that I think is needed. Dump before GVN: *** IR Dump Before Global Value Numbering *** ; Function Attrs: minsize optsize define i16 @TEST__MAIN(i16 %argc.13.par, i16** %argv.14.par) #0 { %buf.17 = alloca [10 x i16], align 1 %_tmp30 = getelementptr inbounds [10 x i16], [10 x i16]* %buf.17, i16 0, i16 0, !dbg !22 call