similar to: [LLVMdev] Tablegen binary literals

Hi Adam > On Jul 30, 2014, at 10:28 PM, Adam Nemet <anemet at apple.com> wrote: > > Hi Pete, > > Just to clarify, are you proposing two things here? First, 0b… literals to have type bits<n> and second to allow bits<n> initializer to contain other bits<m> elements which would initialize the next m elements. > Yeah, exactly those 2 things. I have them

On Thu, Jul 31, 2014 at 12:28 AM, Adam Nemet <anemet at apple.com> wrote: > > On Jul 30, 2014, at 10:56 PM, Pete Cooper <peter_cooper at apple.com> wrote: > > Hi Adam > > On Jul 30, 2014, at 10:28 PM, Adam Nemet <anemet at apple.com> wrote: > > Hi Pete, > > Just to clarify, are you proposing two things here? First, 0b… literals > to have type

On Thu, Jul 31, 2014 at 10:08 AM, Pete Cooper <peter_cooper at apple.com> wrote: > > On Jul 31, 2014, at 9:02 AM, Sean Silva <chisophugis at gmail.com> wrote: > > I think it would make sense to change this behavior to follow the behavior > that Pete describes. I don't have the code handy but my guess is that what > the code is doing here is requesting each

On Thu, Jul 31, 2014 at 12:31 AM, Tim Northover <t.p.northover at gmail.com> wrote: > > Yeah, exactly those 2 things. I have them in separate patches, but I > think > > we only get the benefit from sized binary literals if we also allow them > to > > initialize multiple bits in another bits<n> type. > > It also allows type checking for single

Hi Joe, Le 11/05/2012 02:13, Joe Matarazzo a écrit : > I've been unable to come up with the TableGen recipe to match a > negated operand. My target asm syntax allows the following transform: > > FNEG r8, r5 > MUL r6, r8, r9 > > to > > MUL r6, -r5, r9 > > Is there a Pattern<> syntax that would allow matching *any* opcode (or > even some

Hi, A question from r162999 changes: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?r1=162999&r2=162998&pathrev=162999 For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and "MemOp4" like those of "rm" or "rr" ? multiclass fma4s< > ... def mr : FMA4<opc, MRMSrcMem, (outs

In BPF, an ADD instruction is defined as a 2 register instruction: 0x0f. add dst, src. dst += src In BPFInstrInfo.td this kind of ALU instruction is defined with: def _rr : ALU_RR<BPF_ALU64, Opc, (outs GPR:$dst), (ins GPR:$src2, GPR:$src), "$dst "#OpcodeStr#" $src", [(set

Hi all, I am trying to implement an instruction with no operand for example "clr" in TableGen. ----------------------------------------- e.g. *InstrInfo.td:* class TestInst<string opc, string asmstr, dag oops, dag iops, list<dag> pattern> : Instruction { ... } def int_no_operand : Intrinsic<[]>; class ALU<string opc> : TestInst<opc,

Is it legal to do something like a !strconcat on a non-string entity? That is, is there some operation that will let me do this (replace SOME_CONCAT with an appropriate operator): (WARNING! Hacked-up tablegen ahead!) multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, SDNode OpNode> { // Vector operation emulating scalar (fp)

In the midst of making TableGen Inits unique, I've run into some very odd DenseMap behavior. I converted the TernOpInit to use a factory method that uses a DenseMap to unique objects. I have defined a DenseMapInfo for std::string that uses HashString from StringExtras.h. const TernOpInit *TernOpInit::get(TernaryOp opc, const Init *lhs, const Init *mhs,

On Mar 23, 2009, at 5:56 PM, David Greene wrote: > Is it legal to do something like a !strconcat on a non-string > entity? That > is, is there some operation that will let me do this (replace > SOME_CONCAT with > an appropriate operator): I don't get it, can you try a simpler example on me? :) -Chris > > > (WARNING! Hacked-up tablegen ahead!) > >

On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: ... > For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and > "MemOp4" like those of "rm" or "rr" ? > Hey Anitha, The VEX.W bit is used to denote operand order. In other words, this bit allows for a memop to be used as

On 8 November 2012 11:12, Cameron McInally <cameron.mcinally at nyu.edu> wrote: > On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com> > wrote: > ... >> >> For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and >> "MemOp4" like those of "rm" or "rr" ? >

I've been unable to come up with the TableGen recipe to match a negated operand. My target asm syntax allows the following transform: FNEG r8, r5 MUL r6, r8, r9 to MUL r6, -r5, r9 Is there a Pattern<> syntax that would allow matching *any* opcode (or even some subset), not just MUL, with a FNEG'd operand? I expect I can define a PatFrag: def fneg_su : PatFrag<(ops

On Tuesday 24 March 2009 10:43, Chris Lattner wrote: > On Mar 23, 2009, at 5:56 PM, David Greene wrote: > > Is it legal to do something like a !strconcat on a non-string > > entity? That > > is, is there some operation that will let me do this (replace > > SOME_CONCAT with > > an appropriate operator): > > I don't get it, can you try a simpler example on

On Thursday 11 June 2009 12:28, Chris Lattner wrote: > On Jun 9, 2009, at 12:39 PM, David Greene wrote: > > On Tuesday 09 June 2009 14:34, Dan Gohman wrote: > >> Can you describe what problem you're trying to solve here? Does it > >> really need Regular Expressions? > > > > Yes. I want TableGen to be able to infer lots of stuff > >

Hello! I have some questions about Wine and how/if it can be used with industrial communication like OPC (MicroSoft Com/DCom objects, DDE and more) My short question is: Can I use Wine to make OPC communication work with a Linux system. OPC "OLE for Process Control" A "general" standard for communication in industrial systems, that unfortunately is totally depending on

Colleagues ---------------------------------- System info: R version rw1020 on NT ESS using emacs ver. 20.4 ---------------------------------- To keep my scripts short and tidy, I want to call sub-functions and return variables from these for subsequent use in the calling function. e.g. "test.smooth.opc.time.series" <- function() { load.opc.ascii.files() }

On Jun 11, 2009, at 2:01 PM, David Greene wrote: > On Thursday 11 June 2009 12:28, Chris Lattner wrote: >>> >>> Yes. I want TableGen to be able to infer lots of stuff >>> programmatically. >>> This helps tremendously when specifying things like, oh, AVX. :) >> >> I don't see how this relates to regex's, and really don't want to

Hi Rail, We used a very simple pattern expansion (actually, not a pattern fragment). For example, for AND, ADD (horizontal sum), OR and XOR of 4 elements we use something like the following TableGen structure: class HORIZ_Op4<SDNode opc, RegisterClass regVT, ValueType rt, ValueType vt, string asmstr> : SHAVE_Instr<(outs regVT:$dst), (ins VRF128:$src),