Displaying 20 results from an estimated 20000 matches similar to: "[LLVMdev] MCFixup for distance from instruction to end of .text section"
2013 Aug 19
1
[LLVMdev] Offset in MCFixup
Hi,
I'm trying to implement a 10-bit relocation that does not start at the beginning of a byte-boundary and I'm not entirely sure I understand the use by some targets of MCFixup.Offset and MCFixupKindInfo.TargetOffset.
LLVM's documentation states that:
MCFixup.Offset -"/// The byte index of start of the relocation inside the encoded instruction."
2012 Mar 22
2
[LLVMdev] Sorting relocation entries
Hi Akira,
This is looking good. Some specific comments on the details below.
Thanks!
Jim
> diff --git a/include/llvm/MC/MCELFObjectWriter.h b/include/llvm/MC/MCELFObjectWriter.h
> index 6e9f5d8..220ecd0 100644
> --- a/include/llvm/MC/MCELFObjectWriter.h
> +++ b/include/llvm/MC/MCELFObjectWriter.h
> @@ -13,6 +13,7 @@
> #include "llvm/MC/MCObjectWriter.h"
>
2012 Mar 23
0
[LLVMdev] Sorting relocation entries
Hi Jim,
Thanks for reviewing the patch.
I couldn't get rid of STLExtras.h, but other than that, I followed all
the suggestions in your email.
Please let me know if you notice anything else that needs fixing.
On Thu, Mar 22, 2012 at 4:42 PM, Jim Grosbach <grosbach at apple.com> wrote:
> Hi Akira,
>
> This is looking good. Some specific comments on the details below.
>
>
2012 Mar 23
1
[LLVMdev] Sorting relocation entries
Hi Akira,
Just two very minor things that I missed the first time around.
1. The 'fixup" member of ELFRelocation entry should be "Fixup" instead.
2. Since we're always passing in a non-NULL fixup, that should probably be a reference, not a pointer.
Good for commit with those tweaks.
Thanks!
-Jim
On Mar 23, 2012, at 1:07 PM, Akira Hatanaka wrote:
> Hi Jim,
>
2013 Dec 12
3
[LLVMdev] [RFC PATCH 1/2] x86: Fix ModR/M byte output in 16-bit addressing mode
This attempts to address http://llvm.org/bugs/show_bug.cgi?id=18220
It also fixes a test which was requiring the *wrong* output.
I'm relatively happy with this part, and it even solves most of the hard
part of feature request for .code16 in bug 8684 — which was actually why
I started prodding at this. But I could do with some help with the
16-bit signed relocation handling, which I've
2012 Mar 22
0
[LLVMdev] Sorting relocation entries
Here is the patch.
On Thu, Mar 22, 2012 at 11:11 AM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Hi Jim,
>
> Yes, the relocation entries have to be reordered so that the
> got16/lo16 or hi16/lo16 pairs appear consecutively in the relocation
> table. As a result, relocations can appear in a different order than
> the instructions that they're for.
>
> For
2010 Oct 21
5
[LLVMdev] [llvm-commits] Fwd: Proof of concept patch for unifying the .s/ELF emission of .ARM.attributes
> Also what is the preferred method for MC way of setting out subsection
> sizes after the fact? I am guessing I need to use an MCFixup?
> How do I get an MCExpr to evaluate a method for the subsection size?
> Is there an equivalent use in the places using MCFixup?
> Do I need to add a new subclass to MCExpr for doing this?
>
> JimG, can you please comment on the MachO
2011 Nov 15
0
[LLVMdev] MCELFStreamer subclassing
So what I am hearing is that I should add the following to MC/MCFixup.h:
FK_GPRel_1, ///< A one-byte pc relative fixup.
FK_GPRel_2, ///< A two-byte pc relative fixup.
FK_GPRel_4, ///< A four-byte pc relative fixup.
FK_GPRel_8, ///< A eight-byte pc relative fixup.
In MC/MCStreamer.cpp MCStreamer::EmitGpRel32Value()
Figure out how to mark it with the imprint of
2012 Mar 22
2
[LLVMdev] Sorting relocation entries
Hi Jim,
Yes, the relocation entries have to be reordered so that the
got16/lo16 or hi16/lo16 pairs appear consecutively in the relocation
table. As a result, relocations can appear in a different order than
the instructions that they're for.
For example, in this code, the post-RA scheduler inserts an
instruction with relocation %got(body_ok) between %got(scope_top) and
%lo(scope_top).
$ cat
2010 Oct 21
0
[LLVMdev] [llvm-commits] Fwd: Proof of concept patch for unifying the .s/ELF emission of .ARM.attributes
On Thu, Oct 21, 2010 at 7:50 AM, Rafael Espíndola
<rafael.espindola at gmail.com> wrote:
>> Hmm, I wish we had this discussion way earlier..
>>
>> How would I emit things in different subsections? I can do a high
>> level switch to .ARM.attributes, and if I were emitting one blob from
>> begin to end, using the higher level interface would be preferable,
2011 Nov 15
2
[LLVMdev] MCELFStreamer subclassing
On Tue, Nov 15, 2011 at 11:06 AM, Jim Grosbach <grosbach at apple.com> wrote:
>
> On Nov 15, 2011, at 10:36 AM, Carter, Jack wrote:
>
>> Jim,
>>
>> Ok, you are where I am in the understanding. This is exactly what I do for relocations applied to code. Now I want to apply fixup information to relocations applied to data.
>>
>> The issue I was having was
2011 Oct 10
2
[LLVMdev] Adding fixups and relocations late in code generation
Gang,
I'm tasked with direct object generation for Mips and am trying to not
hack the code.
I how exactly does one set an expression to be PC relative and if the
compiler can resolve it, not produce a relocation?
In our case, the backend produces an expression for the branch which is
the target label. I make a call from the .td for the branch instruction
which calls a routine in
2018 Jul 14
2
Lowering a reasonably complex struct seems to create over complex and invalid assembly fixups on some targets
When I compile this LLVM IR….
@0 = private constant [19 x i8] c"V4main10Brightness\00", section "__TEXT,__swift3_typeref, regular, no_dead_strip"
@1 = private constant [9 x i8] c"Vs5UInt8\00", section "__TEXT,__swift3_typeref, regular, no_dead_strip"
@2 = private constant [18 x i8] c"currentBrightness\00", section "__TEXT,__swift3_reflstr,
2011 Jan 19
1
[LLVMdev] Possible issue with ARM/MC/MachO fixup
Hi everyone.
In ARMAsmBackend.cpp, in routine DarwinARMAsmBackend::ApplyFixup()
there is a curious call to getFixupKindNumBytes() - which can return
1,2, 3, or 4 depending upon the FixupKind
The code in ApplyFixup() seems to be lifted from the X86.
AFAIK, the initial Fixup.Offset() is always divisible by 4, at least
for ARM mode - i.e. it is always at the instruction boundary.
it looks like
2016 Feb 29
2
Possible Memory Savings for tools emitting large amounts of existing data through MC
On Mon, Feb 29, 2016 at 3:36 PM, Peter Collingbourne <peter at pcc.me.uk>
wrote:
> Hi David,
>
> The way I imagined that we might want to extend the MCStreamer API (this
> was motivated by DIEData) is by allowing clients to move bytes and fixups
> into the MC layer.
>
> This is the sort of API that I was imagining:
>
> void
2013 Sep 25
1
[LLVMdev] arm64 / iOS support
Attached is a working patch set for llvm to be able to emit arm64
(currently as triple aarch64-apple-ios) mach-o object files, in case
someone is interested. I'm not sure if the llvm maintainers want the
patch given the previous message that there's going to be an official
patch set from apple to support this, but here is mine.
What works (tested on an iPhone 5S):
* objc strings,
2011 Nov 15
0
[LLVMdev] MCELFStreamer subclassing
On Nov 15, 2011, at 10:36 AM, Carter, Jack wrote:
> Jim,
>
> Ok, you are where I am in the understanding. This is exactly what I do for relocations applied to code. Now I want to apply fixup information to relocations applied to data.
>
> The issue I was having was the difficulty of subclassing MCELFStreamer. Or are you saying that I should be messing with the base MCELFStreamer
2017 Aug 26
2
Error in generating Object Code for implemented assembly vector instructions
i want to emit binary code for the following implemented vector assembly
instructions.
P_256B_LOAD_DWORD R_0_R2048b_0, pword ptr [rip + b]
P_256B_LOAD_DWORD R_0_R2048b_1, pword ptr [rip + c]
P_256B_VADD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_0
P_256B_STORE_DWORD pword ptr [rip + a], R_0_R2048b_0
I added the following lines in X86MCInstLower.cpp;
unsigned NewOpc;
switch (OutMI.getOpcode())
2016 Feb 29
0
Possible Memory Savings for tools emitting large amounts of existing data through MC
Hi David,
The way I imagined that we might want to extend the MCStreamer API (this
was motivated by DIEData) is by allowing clients to move bytes and fixups
into the MC layer.
This is the sort of API that I was imagining:
void MoveAndEmitFragment(SmallVectorImpl<char> &&Data,
SmallVectorImpl<MCFixup> &&Fixups);
Note that this mirrors the
2013 Dec 10
1
[LLVMdev] Support for delayed constants in ARM integrated assembler
I have some assembly code that uses .equ to set a symbol to a computed
constant. It works in GCC but not LLVM. I am not sure about the correct
terminology, but here is an example:
.syntax unified
.set size, end - start
add r0, r0, #size
start:
.space 0x10
end:
GCC will compile this to `add r0, r0, #16`. Compiling with llvm-mc gives:
set.s:4:13: error: invalid operand for