similar to: [LLVMdev] [PATCH][REQUEST] Could someone submit this CSR Kalimba definitions patch please?

Displaying 20 results from an estimated 200 matches similar to: "[LLVMdev] [PATCH][REQUEST] Could someone submit this CSR Kalimba definitions patch please?"

2014 Jul 10
2
[LLVMdev] [PATCH][REQUEST] Could someone submit this CSR Kalimba definitions patch please?
Eric Christopher wrote: > On Wed, Jul 9, 2014 at 11:39 AM, Jonathan Roelofs > <jonathan at codesourcery.com> wrote: >> >> On 7/9/14, 12:33 PM, Eric Christopher wrote: >>> Any reason why you deleted code that isn't related? >>> >>> -eric >>> >>>> - enum SubArchType { >>>> - NoSubArch, >>>> -
2014 Jul 09
2
[LLVMdev] [PATCH][REQUEST] Could someone submit this CSR Kalimba definitions patch please?
On 7/9/14, 12:33 PM, Eric Christopher wrote: > Any reason why you deleted code that isn't related? > > -eric > >> - enum SubArchType { >> - NoSubArch, >> - >> - ARMSubArch_v8, >> - ARMSubArch_v7, >> - ARMSubArch_v7em, >> - ARMSubArch_v7m, >> - ARMSubArch_v7s, >> - ARMSubArch_v6, >> -
2010 Jan 26
1
samba4 HEAD: unable to provision
I'm trying to install samba4 with openldap, as from http://wiki.samba.org/index.php/Samba4/LDAP_Backend/OpenLDAP, I have got the yesterday realease, last git commit: commit 2024d4fb27514869d78e9bb39085f98e80413529 Date: Mon Jan 25 12:41:48 2010 +0100 My system is GNU/Debian Linux Lenny. ./configure --prefix=/opt/samba4 make sudo make install all worked ./setup/provision from the source4
2008 Nov 23
1
Speex DSP porting
Hello Developers, I am considering using SPEEX on an embedded processor that is in fact a DSP with fixed point 24 bit resolution. This DSP is named 'Kalimba' and is present in CSR's product: BLUECORE5. I'm very interested if anybody can tell me if porting is possible (in fact if there are sufficient resources) for implementing a real-time encoding-decoding (duplex). I'm
2014 Sep 09
2
[LLVMdev] Machine Code for different architectures
Hi, We have some DSP architectures (kalimba) which have 24-bits as their "minimum addressable unit". So this means that the sizeof a char (and an int and a short for that matter) is 24-bits. I quickly read the posted link WritingAnLLVMBackend.html but did not see an obvious answer to the following question: Is it possible to write a backend that faithfully represents these
2013 Jul 16
0
[LLVMdev] [PATCH 2/2] X86: infer immediate forms of bit-test instructions
The instruction mnemonics for the immediate forms of bit-test instructions including bt, btr and bts, btc do not work. llvm-mc barfs with: error: ambiguous instructions require an explicit suffix This is highly user-unfriendly, since we can easily infer what the user meant by inspecting $imm and translating the instruction appropriately. Do it exactly as the Intel manual describes. Note that
2014 Sep 09
3
[LLVMdev] Machine Code for different architectures
Hi Johnny, Thanks for this - particularly the tip about cfe-dev. I'm currently trying to coerce lldb to debug these type of architectures (our current toolchain already outputs good dwarf info). However, I'm struggling since lldb has just assumes that the size of a byte is universally 8-bits. At some stage, I *think* at some stage we'd like to derive a compiler, from the "same
2015 Sep 01
0
Anyone ports Opus to CSR Kalimba DSP?
Hi All, Wondering if you or you know some one has done the porting from Opus C reference design to the Assembly of CSR Kalimba DSP? We are working porting and would like to ask more people ( consultant) to join the effort. Thanks, Z -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.xiph.org/pipermail/opus/attachments/20150901/6ba11a06/attachment.htm
2009 Sep 17
1
RFC: edit-livecd.py
This script replaces the existing script in ovirt-node-image to edit live cds. I am Looking for comments/feedback before I send to livecd-list for possible inclusion into Livecd-tools. -D -------------- next part -------------- A non-text attachment was scrubbed... Name: edit-livecd.py Type: text/x-python Size: 11863 bytes Desc: not available URL:
2014 Mar 02
0
3/2/2014 Samba4 git pull make clean error
Hi, I did a git pull and gmake clean give me error: root at www:/usr/local/samba-master # gmake clean WAF_MAKE=1 python ./buildtools/bin/waf clean Selected embedded Heimdal build /usr/local/samba-master/wscript: error: Traceback (most recent call last): File "/usr/local/samba-master/buildtools/wafadmin/Utils.py", line 647, in recurse exec(compile(txt, file_path,
2014 Sep 10
2
[LLVMdev] Machine Code for different architectures
Hi Patrik, Thanks for this note. It's encouraging to read there has been some provision made for non-8-bit bytes. I'm not a compiler/backend expert, (although maybe I'll need to be soon!), so I won't look at the patches right now, however may at some stage in the future myself or colleague may request these patches from yourself. Yes, our 24-bit architectures have non-power-of-2
2016 Jan 03
2
Diff to add ARMv6L to Target parser
Hi all. I’ve been working with Swift on ARMv6 and v7. While working with ARMv6 on linux, I noticed that my arm architecture canonicalization code didn’t produce the expected result. The code that I had been using (within Swift’s Driver.cpp the following: static llvm::Triple computeTargetTriple(StringRef DefaultTargetTriple) { llvm::Triple triple = llvm::Triple(DefaultTargetTriple); //
2015 Apr 15
2
[LLVMdev] About the "debugger target"
While I've already posted reviews for the initial patches for this (see http://reviews.llvm.org/D8506 and http://reviews.llvm.org/D8599), the grapevine suggests I should post a lengthier description of my intent for the "debugger target." The idea was prompted by a suggestion from Eric Christopher, and I'm running with it. Various bits of the DWARF we produce are conditional on
2014 Sep 09
2
[LLVMdev] Machine Code for different architectures
How does LLVM generate machine code for different architectures? For example, the machine code for x86 and amd will vary. How does LLVM convert its IR to machine code for different architectures.Can you please explain the approach? Is it just write two different programs for two different architectures and pass a flag to the compiler based on which machine code you want to generate? Thanks a lot
2011 Aug 03
0
[PATCH] display ipv6 address in networking details page, also fix ipv6 netmask configurations.
rhbz#698650 Signed-off-by: Joey Boggs <jboggs at redhat.com> --- scripts/network.py | 3 +- scripts/ovirt-config-setup.py | 46 +++++++++++++++++++++++++++++++++------- scripts/ovirtfunctions.py | 22 +++++++++++-------- 3 files changed, 53 insertions(+), 18 deletions(-) diff --git a/scripts/network.py b/scripts/network.py index ccc4bd8..f51ee7c 100644 ---
2011 Jul 20
0
[PATCH] fix ipv4 static/dhcp/disabled networking changes
This fixes networking changes when switching from dhcp/static to disabled. Before the ifcfg scripts would contain old values from the previous configuration. Support for disabled devices is now added and some useless remnant bash->python coding cleaned up --- scripts/network.py | 45 +++++++++++++++++++--------------------- scripts/ovirt-config-setup.py | 34
2014 Feb 13
2
[LLVMdev] Bad test health
I was curious how widespread bad usage of FileCheck prefixes is in the LLVM/Clang test suite. Running the attached script yields over 200 tests (~1.5%) which are essentially broken because they contain checks that are never checked. Most widespread is the usage of the "CHECK" prefix while all FileCheck invocations have an explicit check prefix. Then there are quite a few prefixes that
2011 Aug 03
1
[PATCH] display ipv6 address in networking details page, also fix ipv6 netmask configurations
rhbz#698650 Signed-off-by: Joey Boggs <jboggs at redhat.com> --- scripts/network.py | 3 +- scripts/ovirt-config-setup.py | 48 ++++++++++++++++++++++++++++++++++------ scripts/ovirtfunctions.py | 20 ++++++++++------ 3 files changed, 54 insertions(+), 17 deletions(-) diff --git a/scripts/network.py b/scripts/network.py index ccc4bd8..f51ee7c 100644 ---
2014 Aug 19
2
[LLVMdev] llvm::Triple support for haswell-enabled x86_64
I'm working on LLDB and we have a bunch of code that is manually manipulating triples and doing a bunch of nasty stuff to account for the fact that llvm::Triple doesn't currently have a way to detect x86_64h. Is this something that llvm::Triple could be modified to support? Either as a new ArchType, or a new SubArchType? -------------- next part -------------- An HTML attachment was
2015 Jul 29
5
[LLVMdev] The Trouble with Triples
> > The Triple object will remain unchanged. > > The Tuple will be the API to handle getting/setting parameters > depending on the Triple, compiler flags, attributes, etc. > > This part doesn't seem obvious from the direction the patches are going. > There will be no string representation of all options, as that would > be impossible, or at least, highly