similar to: [LLVMdev] codeGen, instruction write one value to the input register.

Tks Cameron, I did some study on it. Now I am having the same problem as mentioned in this thread;"http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-January/057654.html” , > Looking at the X86 back-end code, it looks like there do exist > multi-output instructions, but they all use physical (implicit) registers > for the second destination, not arbitrary register types. And if I

Hi All, In XCore backend, I saw “ …... EVT VT = Op.getValueType(); SDValue Data = DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3)); SDValue Crc(Data.getNode(), 1); SDValue Results[] = { Crc, Data }; return DAG.getMergeValues(Results, 2, DL); “ which is used to lower an

Hi guys, I just noticed that the LLVM has some node for signed/unsigned type( like udiv, sdiv), but why the ADD, SUB do not have the counter part sadd, uadd? best kevin

Hi Guys, I see an intrinsic function call like this "call float @ir.sample_complex.f32(float a, int bitcast (i16 337203 to i32) , i32 1, <2 x float> %62, float %61) “, Then I got trouble to process the third operand "int bitcast (i16 337203 to i32)”, the second operand I got is “constant 337203”. I think something is messed up, but the getOperand(i) is llvm core function.

Tks Tom, That is my confusing part. How can I make it to "access memory” so it will HasChain? Is there any flag set like in typeProfile, Node, instructions? myLoad, mayStore, SDNPHasChain? -kevin On Jul 18, 2014, at 4:26 PM, Tom Stellard <tom at stellard.net> wrote: > On Fri, Jul 18, 2014 at 04:15:45PM -0400, kewuzhang wrote: >> sure! >> >> class

So if the overflow happens for either one of the case, the return value will be implementation dependent? best kevin On Feb 17, 2015, at 2:01 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Kevin, > > On 17 February 2015 at 10:41, kewuzhang <kewu.zhang at amd.com> wrote: >> I just noticed that the LLVM has some node for signed/unsigned type( like udiv,

On Jul 31, 2014, at 7:23 PM, Tom Stellard <tom at stellard.net> wrote: > On Thu, Jul 31, 2014 at 06:41:06PM -0400, kewuzhang wrote: >> Hi All, >> >> Is it possible to initialize(set up) register attributes when we define an instruction? >> >> like >> >> if a register is defined like this: >> >> " class

Hi guys, In X86ISelLowering.cpp I saw” ... case Intrinsic::x86_rdrand_16: case Intrinsic::x86_rdrand_32: …. case Intrinsic::x86_avx512_gather_qpd_512: case Intrinsic::x86_avx512_gather_qps_512: .. “ those intrinsics are handled by “LowerINTRINSIC_W_CHAIN”. How the “INTRINSIC_W_CHAIN” opCode is set instead of “INTRINSIC_WO_CHAIN”? tks Kevin -------------- next part -------------- An

Hi Guys, I am trying to promote half to float for my intrinsic math operations, following class and pattern are defined. " class S_HF__HF< string asmstr> : Intrinsic <[llvm_float_ty ], [llvm_float_ty ], [IntrNoMem], !strconcat(asmstr, "_f16")>; def :Pat<( f16 (int_my_math_f16 f16:$src)), (F2Hsr (FEXTsr f16:$src) )>; “ where FEXTsr is

Hi guys, I am working on an intrinsic function, which will write to a pointer argument. So I am lowering it and think I need to catch it in lowerINTRINSIC_W_CHAIN, but somehow it always fall into INTRINSIC_WO_CHAIN category. I put [IntrReadwriteArgMem] into my Intrinsic class definition, it did not help. tried put [SDNPHasChain] into intrinsic class definition, cause errors” Element type

Hi Guys, I noticed that the operation actions( promote/expand/custom) are set per operation basis. Wondering if we can set it up globally? For example, I have native supported 32 bits registers, to handle 8 bits value operations, I want to do promote. and to support 64 bit operations, I want to expand. If I can set up the operation actions for the same type globally, then I can avoid to

Dear there, I have a target which is supporting the 32 bit operations natively. Right now,I want to make it support the 16 bits operations as well. My initial thought is: (1) I can adding something like “ CCIfType< [i16], CCPromoteToType<i32>>”, to the CallingConv.td, then “all” the 16 bits operands will be automatically promoted to 32 bits, it will be all set. but looks it is not

sure! class TEST_INTINSIC_FM< string asmstr> : Intrinsic <llvm_i32_ty], [llvm_i32_ty, llvm_ptr_ty], [IntrReadWriteArgMem], !strconcat(“llvm.test”, asmstr),”.float”) >; tks On Jul 18, 2014, at 4:06 PM, Tom Stellard <tom at stellard.net> wrote: > On Fri, Jul 18, 2014 at 03:19:47PM -0400, kewuzhang wrote: >> en! >> >> my test is : %r1 =

Hi Guys, I and trying to covert a float to a f16. calling DAG.getNode(ISD::FP_ROUND, DL, Op->getValueType(0), FloatNode); will get the error message:"Invalid method to make FP_ROUND node" what is the "right" way to make this work? best Kevin -------------- next part -------------- An HTML attachment was scrubbed... URL:

en! my test is : %r1 = call<float> @test.adddiv( <float> %r0, <float>* %p0). since >> but somehow it always fall into INTRINSIC_WO_CHAIN category. (caught it in lowering..) I think it doesn’t have chain in initial DAG. unfortunately the intrinsic “test.adddiv” is defined by me for now. not sure how to make it has a chain. kevin On Jul 18, 2014, at 3:06 PM,

Yeah. I agree that "Chain operand is needed if the intrinsic is reading / writing memory.”, Just don’t know where and how to set it up. like intrinsic “int_x86_xtest: “ def int_x86_xtest : GCCBuiltin<"__builtin_ia32_xtest">, Intrinsic<[llvm_i32_ty], [], []>; “ "def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0,

Hi All, Is it possible to initialize(set up) register attributes when we define an instruction? like if a register is defined like this: " class SC_Register<bits<8> register_num, REG_FLAG SC_X, REG_FLAG SC_Y, REG_FLAG SC_Z, REG_FLAG SC_W, string asmstr> : Register<asmstr> { let HWEncoding{7-0} =

I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns. What I am trying to do is take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace =

I'm not at the machine that has the changes, but it was failing at index 0. Micah From: Owen Anderson [mailto:resistor at mac.com] Sent: Thursday, April 19, 2012 3:35 PM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output

Hi Guys, I have a taget instruction which take a vec4 and returns a vec4.( say instruction “vec4:$dst mod( vec4:$src)" ) And I want to use it to match i an ir instruction/intrinsic function( say " float:$dst llvm.irmod( vec4:$src)" which takes a vec4, output a float. I think the procedure is: when I see the intrinsic llvm.irmod, I need to call "extractlt(