similar to: [LLVMdev] How to add a MVT::Glue property of intrinsic node?

On Jan 3, 2014, at 11:01 AM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 3, 2014, at 4:58 AM, Haishan <hndxvon at 163.com> wrote: > >> >> At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: >> >> On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: >> My update steps are shown

At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level

On Jan 4, 2014, at 4:38 AM, Haishan <hndxvon at 163.com> wrote: > At 2014-01-04 06:11:38,"Jakob Stoklund Olesen" <stoklund at 2pi.dk> wrote: > > On Jan 3, 2014, at 1:52 PM, Andrew Trick <atrick at apple.com> wrote: > >> He really just wants to rerun LiveIntervals analysis, but LiveVariables is no longer available. Would it work just to clear all

At 2013-12-15 22:43:34,"Caldarale, Charles R" <Chuck.Caldarale at unisys.com> wrote: >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] >> On Behalf Of Haishan >> Subject: [LLVMdev] Question about Pre-RA-schedule in LLVM3.3 > >> My clang version is 3.3 and debug build. > >> //test.c >> int a[6] = {1, 2, 3, 4, 5,

On Jan 3, 2014, at 1:06 PM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 3, 2014, at 12:10 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > >> >> On Jan 3, 2014, at 11:01 AM, Andrew Trick <atrick at apple.com> wrote: >> >>> >>> On Jan 3, 2014, at 4:58 AM, Haishan <hndxvon at 163.com> wrote: >>>

The flag -enable-aa-sched-mi should do what you want you want in the MachineScheduler pass. If you want to do it in the selection DAG, there is a subtarget hook that might do it: TargetSubtargetInfo::useAA() LLVM won’t generate the schedule you want anyway for Intel core processors, but the alias analysis can be useful in general. -Andy On Dec 16, 2013, at 6:03 AM, Haishan <hndxvon at

Hello everyone, I wanted to attach a node without affecting the present nodes in any way. I tried to use MVT::Glue for that but I think I'm missing something as I could not achieve the below state. LUI LUI | | ADDI ----GLUE---- ADDI | store I've few question about this and Glue node in general, I'll be happy to get some help on

Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probable reason of this error is that no LiveInterval information for newly MBB which is used by Register Allocation. And, LiveIntervals depend

The log message for revision 122213 says: > Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which > their carry depenedencies with MVT::Flag operands) and use clean and beautiful > EFLAGS dependences instead. (MVT::Flag has since been renamed to MVT::Glue.) That revision made bug 8404 go away. Am I right in thinking that one of the problems with MVT::Glue is

On Jan 3, 2014, at 1:52 PM, Andrew Trick <atrick at apple.com> wrote: > He really just wants to rerun LiveIntervals analysis, but LiveVariables is no longer available. Would it work just to clear all the intervals rerun LiveIntervals::computeVirtRegs after all the CFG transforms are complete? Yes, I should think so. /jakob -------------- next part -------------- An HTML attachment was

Hi, I'm not sure. But in your lowered DAG the chain nodes are the first operands for you custom nodes, however for the other nodes the chain is the last operand. I seem to remember that during targetlowering the chain is the first operand and then it seems to switch over after ISelDAG, this confused me and may have something to do with the issue that you are seeing. I really don't

Hi, Thanks for your answer. I am looking for a map, and the data structure of this map is map<const Instruction *, vector<MachineInstr*> > In this map, its keyvalue is IR instruction pointer, and its second value is a container which is composed of MachineInstr lowering by its keyvalue. For example: IR Instruction %0 = load i32* getelementptr inbounds ([6 x i32]* @a, i32 0,

On 03/14/2017 07:16 AM, vivek pandya wrote: > Hello Hal, > setCondCodeAction(expand) for un ordered comparison generates > semantically wrong code for me for example SETUNE gets converted to > SETOE that causes infinite loops. Can you please explain what is happening? It sounds like a bug we should fix. > > What is ideal place where I can convert unordered comparison to un

Hi, I got that message from a call to InstrEmitter::AddOperand. I am writing a back end for CortexM0 (for self teaching purposes), I am working on LDR with immediate offset instruction. In the ARM backend, if the offset is 0, the following code is executed by the function ARMDAGToDAGISel::SelectThumbAddrModeImm5S Base = N.getOperand(0); OffImm = CurDAG->getTargetConstant(0, MVT::i32);

Hello. I am using the post-RA (Register Allocation) scheduler to avoid data hazards by inserting other USEFUL instructions from the program (besides NOPs) and it breaks apart some sequences of instructions which should remain "glued" together. More exactly, in my [Target]ISelDAGToDAG.cpp it is possible that I replace for example a BUILD_VECTOR with a machine SDNode called

Hi guys I got the errors like this while compiling cluster glue: ./.libs/libplumb.so: undefined reference to `uuid_parse' ./.libs/libplumb.so: undefined reference to `uuid_generate' ./.libs/libplumb.so: undefined reference to `uuid_copy' ./.libs/libplumb.so: undefined reference to `uuid_is_null' ./.libs/libplumb.so: undefined reference to `uuid_unparse'

Hola, Estoy haciendo un análisis de datos de Twitter y cuando intento correr esta línea de código: timelines %>% dplyr::filter(created_at > "2020-01-01") %>% dplyr::group_by(screen_name) %>% ts_plot("days", trim = 1L) + ggplot2::geom_point() + ggplot2::labs( title = "Tuits publicados por cada cuenta" ) Me da el siguiente error Error in

Right now the MemSDNode keeps a volatile bit in the SubclassData to mark volatile memory operations. We have some changes we'd like to push back that adds a NonTemporal flag to MemSDNode to mark instructions where movnt (on x86) and other goodness can happen (we'll also add the TableGen patterns to properly select movnt). In our tree we simply added another flag to the MemSDNode

hi, I compile a case (test.c) to get IR file (test.ll) using clang as follows: "clang -emit-llvm -S -O2 test.c -o test.ll" My clang source code version is release 3.3 and debugging build. //test.c int foo(int j) { return ++j > 0; } int main() { if (foo(((~0U)>>1))) abort(); exit(0) } //end test.c Here are the generated IR file: //test.ll ;

Hi, for DAG-to-DAG instruction selection I’ve implemented a pattern, which creates from one SDNode two instructions, something like: def: Pat<(NEW_SDNODE REG:$r1), (INST_OUT (INST_IN), REG:$r1)>; where INST_IN doesn't accepts any inputs and INST_OUT accepts two inputs - one returned by INST_IN and REG;$r1. Is there any possibility to ‘Glue’ two instruction created