similar to: [LLVMdev] Inline Assembly in IR

Dear, I am currently working on one specific architecture. When I make changes and try to "make" it takes a very long time as It compiles all the files in the source. My question is since I am only editing a few files in the architecture directory and some files in include directory, Can I speed up my "make" by running "make" only for a few files? Can such changes

Dear, I have the following problem. I am given 2 instructions say I1 and I2 whose selection should depend on the operands. Say the operands have a boolean attribute 'attr'. I would like to select I1 and I2 by some logic that involves the 'attr' attribute of all the operands involved. eg: If all operands have attr set to True, I want I1 to be selected to operate else I2. How can I

Dear, I am looking at the Instructions defined in the XXXXInstrInfo.td where I can see a def record defined like below def ADD8rr : I8rr<0x0, (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "add.b\t{$src2, $dst}", [(set GR8:$dst, (*add *GR8:$src, GR8:$src2)), (implicit SRW)]>; Now here I would like the to

Dear, I am new to llvm and hence have very little idea about a problem that is my university project. I am supposed to assume a X86 CPU supporting an instruction ADDenc that adds two encrypted operands. The original ADD also exists and should operate on unencrypted operands. My task is to transform C programs into the new X86 assembly that supports ADDenc. I have very little idea about this. I

Dear, I am looking to build a compiler-assembler with a custom architecture. I have a new Instruction set defined with me and I would like atleast my C programs to get converted to assembly language corresponding to the custom architecture. I have been going through llvm and its resources on the web, Can any one of you offer guidance about the above problem. All I want is to develop a tool

Hi all, I'm getting rather odd behavior from a call asm inteldialect(). TL;DR is "mov reg, $0" with a "i" constraint on $0 is behaving identical to "mov reg, dword ptr [$0]" and differently from "movl $0, reg" in AT&T syntax. I'm not sure how to get clang to emit an inteldialect, so for this example, I'm emitting llvm and then modifying

> On Jan 7, 2020, at 18:41, Craig Topper <craig.topper at gmail.com> wrote: > > What version of llvm are you using? This looks like it may be fixed on trunk. After poking at my installation of rust, I'm not entirely sure what version of LLVM it uses. Looking at the GitHub page, it looks like Rust maintains their own copy of llvm and cherry picks commits. The C example was

Hi all, I'm trying to land (a rebased version of) http://llvm.org/D37461 - which should make it possible to handle x86 Intel assembly like mov eax, offset Foo::ptr + 1 (Currently, omitting the +1 works... but offset doesn't work in compound expressions.) I'm having trouble figuring out what inline assembly I can emit into the LLVM IR that will work properly. So far, the closest

Hi all, I'm working for translating dex bytecode to LLVM IR In order to communicate with Android interpreter, The work have to add data below some instructions I want to use inline assembly to add data. Thus, I wrote a little program to find out the related LLVM IR int main() { asm(".long 0x12345678"); return 0; } and I use clang to translate it into bitcode It's the

I encountered this issue of unique asm label names just now, in https://bugs.freebsd.org/216771 . A very simple test case is this: void foo(void) { asm volatile( "named_label:\n" "jnz named_label\n" ); } void bar(void) { foo(); } Compiling this with any form of optimization gives an error, because clang is attempting to inline foo() into

Hey all, I'd like to propose a new intrinsic for use in preventing optimizations from deleting IR due to constant propagation, dead code elimination, etc. # Background/Motivation In Rust we have a crate called `test` which provides a function, `black_box`, which is designed to be a no-op function that prevents constprop, die, etc from interfering with tests/benchmarks but otherwise

Hello, In the following code snippet: %tmp49 = call i64 asm "movq %gs:${1:P},$0", "=r,im,,~{fpsr},~{flags}"(i64* @kernel_stack) #6, !dbg !6625, !srcloc !5841 I would expect for the inline asm call to receive two arguments because of the ${1:P} corresponding to a %P1 that will append the $1 to %%gs:. Can someone explain why there is only one argument in this call? Moreover,

Hello, Most of the IR language is correctly explained; but with inline assembly I feel alone at some point: define i32 @main(i32 %argc, i8** %argv) #0 { ... //some uninteresting bloat here call void asm sideeffect "outw %eax, $0", "imr,~{dirflag},~{fpsr},~{flags}"(i32 %8) #2, !srcloc !2 ret i32 0 } I reduced the above code to the offending line containing:

Using Clang/LLVM 3.6.0 we are observing a case where the optimizations are clobbering EFLAGS on x86_64. This is inconvenient when the status of bit 9 (IF), which controls interrupts, changes. Here's a simple test program. Assume that the external function foo() modifies the IF bit in EFLAGS. --- #include <stdlib.h> #include <stdbool.h> void foo(void); int a; int bar(void)

HI, When compiling the open-source software cryptopp (https://www.cryptopp.com/#download <https://www.cryptopp.com/#download>) version 5.6.4 I found a strange issue with the IR generated. The issue only appears when compiling with -O2 optimisation in the integer.cpp file (the function is _ZN8CryptoPPrsERNSt3__113basic_istreamIcNS0_11char_traitsIcEEEERNS_7IntegerE ->

> On Mar 1, 2015, at 7:53 AM, Björn Steinbrink <bsteinbr at gmail.com> wrote: > > On 2015.02.28 18:17:27 -0800, Philip Reames wrote: >>> On Feb 28, 2015, at 3:01 PM, Björn Steinbrink <bsteinbr at gmail.com> wrote: >>> 2015-02-28 23:50 GMT+01:00 Philip Reames <listmail at philipreames.com>: >>>>>> On Feb 28, 2015, at 2:30 PM, Björn

> On Feb 28, 2015, at 3:01 PM, Björn Steinbrink <bsteinbr at gmail.com> wrote: > > [This time without dropping the list, sorry] > > 2015-02-28 23:50 GMT+01:00 Philip Reames <listmail at philipreames.com>: > >>>> On Feb 28, 2015, at 2:30 PM, Björn Steinbrink <bsteinbr at gmail.com> wrote: >>>> >>>>> On 2015.02.28

On Jul 1, 2011, at 4:08 PM, Jakob Stoklund Olesen wrote: > I want to report a problem with an inline assembly instruction from a code generator pass? > > How can I do that with the proper diagnostic format and source location? > > Right now we only get: > > clang -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c > fatal error: error in backend: Inline

----- Original Message ----- > From: "Diego Novillo" <dnovillo at google.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "Chris Lattner" <clattner at apple.com>, "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Friday, March 7, 2014 8:07:19 AM > Subject: Re: [LLVMdev] RFC - Adding an optimization

[This time without dropping the list, sorry] 2015-02-28 23:50 GMT+01:00 Philip Reames <listmail at philipreames.com>: >> On Feb 28, 2015, at 2:30 PM, Björn Steinbrink <bsteinbr at gmail.com> wrote: >> >>> On 2015.02.28 14:23:02 -0800, Philip Reames wrote: >>>> On 02/28/2015 10:04 AM, Björn Steinbrink wrote: >>>> Hi, >>>>