similar to: [LLVMdev] Help regarding ad new functionality in Backend

I've been unable to come up with the TableGen recipe to match a negated operand. My target asm syntax allows the following transform: FNEG r8, r5 MUL r6, r8, r9 to MUL r6, -r5, r9 Is there a Pattern<> syntax that would allow matching *any* opcode (or even some subset), not just MUL, with a FNEG'd operand? I expect I can define a PatFrag: def fneg_su : PatFrag<(ops

Dear, Can anybody comment on inserting inline assembly in LLVM IR? -- Pratik -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140620/03400e95/attachment.html>

Hi Joe, Le 11/05/2012 02:13, Joe Matarazzo a écrit : > I've been unable to come up with the TableGen recipe to match a > negated operand. My target asm syntax allows the following transform: > > FNEG r8, r5 > MUL r6, r8, r9 > > to > > MUL r6, -r5, r9 > > Is there a Pattern<> syntax that would allow matching *any* opcode (or > even some

Dear, I am currently working on one specific architecture. When I make changes and try to "make" it takes a very long time as It compiles all the files in the source. My question is since I am only editing a few files in the architecture directory and some files in include directory, Can I speed up my "make" by running "make" only for a few files? Can such changes

Dear, I have the following problem. I am given 2 instructions say I1 and I2 whose selection should depend on the operands. Say the operands have a boolean attribute 'attr'. I would like to select I1 and I2 by some logic that involves the 'attr' attribute of all the operands involved. eg: If all operands have attr set to True, I want I1 to be selected to operate else I2. How can I

Preamble -------- While working on an IR-level optimisation completely unrelated to register allocation I happened to trigger some really strange register allocator behaviour causing a large regression in bzip2 in spec2006. I've been trying to fix that regression before getting the optimisation patch committed, because I don't want to regress spec2006, but I'm basically fumbling in

enableAdvancedRASplitCost() does the same thing as ConsiderLocalIntervalCost, but as a subtarget option instead of a command-line option, and as I’ve said it doesn’t help because it’s a non-local interval causing the eviction chain (RAGreedy::splitCanCauseEvictionChain only considers the local interval for a single block, and it’s unclear to me how to make it handle a non-local interval). John

Hi, I tried this as well, using the following line to add function declaration to the caller module. Function::Create(FT, Function::ExternalLinkage, "gcd", mod); Where "FT" is the same as before. And the output produced by the PrintModulePass becomes: ; ModuleID = 'GCDMain' declare i32 @gcd(i32, i32) define i32 @main() { EntryBlock: %tmp = call i32 @gcd(i32

On Wed, Aug 31, 2011 at 10:54 AM, Mian M. Hamayun <mian-muhammad.hamayun at imag.fr> wrote: > Hi, > > I tried this as well, using the following line to add function declaration > to the caller module. > > Function::Create(FT, Function::ExternalLinkage, "gcd", mod); > > Where "FT" is the same as before. And the output produced by the >

I've just begun playing around with defining functions in R and I'm not really sure what's going on in the following situation. I've defined the following function: gcd <- function(x,y) { x <- as.integer(x); y <- as.integer(y) q <- as.integer(x / y) r <- x - q * y if (r==0) y else gcd(y,r) } As expected, it gives the following results: > gcd(3,2) [1] 1

I have a question: In the pattern below from X86 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\tdst", [(set GR8:$dst, (add GR8:$src, 1))]>; Since we are emitting only "inc $dst", What makes sure that the $src and $dst are same register? - Sanjiv

Micah, Do you mean we should make GPR64 available to register allocator by calling addRegisterClass? addRegisterClass(MVT::i64, &GPR64RegClass) If we add register class GPR64, type legalization will stop expanding i64 operations because i64 is now a legal type. Then we will probably have to write lots of code to custom-lower unsupported 64-bit operations during legalization. Note that

On Mips 32 there is traditionally a 64 bit HI/LO register for the result of multiplying two 64 bit numbers. There are corresponding instructions to load the LO and HI parts into individual 32 registers. On Mips with the DSP ASE (an application specific extension), there are actual 4 such pairs of registers. Is there a way to have special purpose 64 bit registers without actually having to

Hi, I'm trying to understand how virtual regs are assigned to operands in IR instructions. I looked into SelectionDAG but could not figure out where the assignment happens. How and where does this conversion happen? Furthermore, I want to build a map between variable and the virtual register (x corresponds to vreg11 in below code). I've been stuck here for a while. Any help is greatly

The target description .td files are allowed to change the default allocation order on a register class by overriding the allocation_order_begin() and allocation_order_end() methods on TargetRegisterClass. Previously, this was used all the time to filter out stack and frame pointers and other reserved registers. I was able to remove most of these custom allocation orders in the tree because the

sanjiv gupta wrote: > I have a question: > In the pattern below from X86 > > def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), > "inc{b}\tdst", > [(set GR8:$dst, (add GR8:$src, 1))]>; > > Since we are emitting only "inc $dst", > What makes sure that the $src and $dst are same register? > > - Sanjiv It's enclosed

Hi, I am creating a new backend for a custom microcontroller. In order to create the backend I am modifying from Mips backend. My architecture has a store instruction with direct address mode. It accepts two arguments: source register and address (immediate). This instruction is not available in Mips, but it is in Hexagon, so I copied from Hexagon the following, adapting it to my registers: -

hi ?integer says: Note that on almost all implementations of R the range of representable integers is restricted to about +/-2*10^9: 'double's can hold much larger integers exactly. I am getting very confused as to when to use integers and when not to. In my line I need exact comparisons of large integer-valued arrays, so I often use as.integer(), but the above

I am working the AVR backend. It is still in the early stage. I got the following error:[ 86%] Building CXX object lib/Target/AVR/CMakeFiles/LLVMAVRCodeGen.dir/AVRISelDAGToDAG.cpp.obj AVRISelDAGToDAG.cpp C:\llvm-build\lib\Target\AVR\AVRGenDAGISel.inc(596) : error C2664: 'llvm::SDNode *llvm::SelectionDAG::SelectNodeTo(llvm::SDNode *,unsigned int,llvm::MVT,llvm::MVT,llvm::MVT,const llvm::SDValue

I see in the x86 InstInfo.td the following for the INC instructions: def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", [(set GR8:$dst, (add GR8:$src, 1))]>; Which seem to have the same restriction that I'm trying to implement, but I don't understand how this ensures that $src and $dst are the same register. -- Christopher Lamb