similar to: [LLVMdev] regarding TargetRegisterInfo.h

Dear Tim, Thank you for replying back. I could find the file. But when I try running tblgen on one of the .td's which has such an include statement I get "file not found error" eg: llvm-tblgen X86.td gives file not found where X86.td has an include statement namely "include "llvm\Target\Target.td". Can you please clear this too? Regards, Pratik On Mon, Jun 9,

Dear, Can anybody comment on inserting inline assembly in LLVM IR? -- Pratik -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140620/03400e95/attachment.html>

Dear, I am currently working on one specific architecture. When I make changes and try to "make" it takes a very long time as It compiles all the files in the source. My question is since I am only editing a few files in the architecture directory and some files in include directory, Can I speed up my "make" by running "make" only for a few files? Can such changes

Dear, I have the following problem. I am given 2 instructions say I1 and I2 whose selection should depend on the operands. Say the operands have a boolean attribute 'attr'. I would like to select I1 and I2 by some logic that involves the 'attr' attribute of all the operands involved. eg: If all operands have attr set to True, I want I1 to be selected to operate else I2. How can I

Dear, I am looking at the Instructions defined in the XXXXInstrInfo.td where I can see a def record defined like below def ADD8rr : I8rr<0x0, (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "add.b\t{$src2, $dst}", [(set GR8:$dst, (*add *GR8:$src, GR8:$src2)), (implicit SRW)]>; Now here I would like the to

Dear, I am looking to build a compiler-assembler with a custom architecture. I have a new Instruction set defined with me and I would like atleast my C programs to get converted to assembly language corresponding to the custom architecture. I have been going through llvm and its resources on the web, Can any one of you offer guidance about the above problem. All I want is to develop a tool

Dear, I am new to llvm and hence have very little idea about a problem that is my university project. I am supposed to assume a X86 CPU supporting an instruction ADDenc that adds two encrypted operands. The original ADD also exists and should operate on unencrypted operands. My task is to transform C programs into the new X86 assembly that supports ADDenc. I have very little idea about this. I

Can you guys post a demo of your application ? Would be great. Thanks, Pratik -- rm -rf / 2>/dev/null - http://null.in

On Nov 27, 2012, at 10:24 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > Would anyone object to my moving the TargetRegisterInfo and TargetInstrInfo classes into libCodeGen? > > TargetInstrInfo is already halfway there with its TargetInstrInfoImpl class implementing most shared functionality. The lib/Target/TargetInstrInfo.cpp file has two remaining functions that happen

Hi, Would anyone object to my moving the TargetRegisterInfo and TargetInstrInfo classes into libCodeGen? TargetInstrInfo is already halfway there with its TargetInstrInfoImpl class implementing most shared functionality. The lib/Target/TargetInstrInfo.cpp file has two remaining functions that happen to not depend on libCodeGen, but I don't think they serve any purpose as part of libTarget.

Would it be possible to increase TargetRegisterInfo::FirstVirtualRegister to something quite a bit larger - such as 2^31? I'm working on a target where all SSA values need to be assigned physical registers, and the current limit of 16384 may limit the size of programs that I'm able to handle. 2^31 is a nice value since there are equal numbers of possible physical and virtual registers,

Hi all, I ran into this while trying to figure out why the X86 getSUBriOpcode/getADDriOpcode functions are duplicated, appearing once in X86RegisterInfo.cpp and once in X86FrameLowering.cpp, The method TargetRegisterInfo::eliminateCallFramePseudoInstr doesn't appear to really belong in this interface. It adds instructions into the MachineFunction given to it, which isn't what

I''m sorry - just couldn''t come up with a subject that describes the problem :( Anyway, this is my problem. I have a long list of fields that need to be displayed when a ''show'' is requested on the controller. I''m now doing the list.rhtml and looking for a DRY way to do the following. For each data item, I have 2 fields - one is the item name, the

I''m having a class called Person, with subclasses as goalkeeper, forward, defender. Now a person can be a forward as well as a defender or a goalkeeper. I want to use single table inheritance like : class Goalkeepr < Person end And not have multiple boolean columns like in my people table like is is_goalkpeer, is_forward, is_defender. How do I go about it ? Thanks, Pratik -- rm

Is there a way by which I can do form validation for form generated by In Place Editting of scritaculous? The reason is, I want to avoid server roundtrip for checks which I can perform at browser. Regards, Jatinder -------------- next part -------------- An HTML attachment was scrubbed... URL: http://wrath.rubyonrails.org/pipermail/rails/attachments/20060828/ca882668/attachment-0001.html

On Nov 27, 2012, at 11:51 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Nov 27, 2012, at 11:23 AM, Chris Lattner <clattner at apple.com> wrote: > >> On Nov 27, 2012, at 10:24 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >>> Would anyone object to my moving the TargetRegisterInfo and TargetInstrInfo classes into libCodeGen?

I''m trying to setup my rails application with Light+fcgi. This is the error I''m getting when I try to start Lighttpd : ============ [getcapture@alpha getcapture]$ ~/etc/rc.d/lighttpd.sh start Starting Lighttpd 2006-04-15 11:27:24: (mod_fastcgi.c.1022) execve failed for: /home/getcapture/application/public/dispatch.fcgi No such file or directory [getcapture@alpha getcapture]$

On Jan 6, 2011, at 10:11 PM, andrew at sidefx.com wrote: > Would it be possible to increase TargetRegisterInfo::FirstVirtualRegister > to something quite a bit larger - such as 2^31? I'm working on a target > where all SSA values need to be assigned physical registers, and the > current limit of 16384 may limit the size of programs that I'm able to > handle. 2^31 is a

To fix some problems with how condition registers are saved/restored for PowerPC, I need to override TargetRegisterInfo::hasReservedSpillSlot() in PPCRegisterInfo. I've had some difficulties because of the constness of the function, and I'm wondering what the best way to handle this would be. Essentially I need to add a field to PPCRegisterInfo, and modify that field in

Hi, ABCRegister.td : def SGPR32 : RegisterClass<"ABC", [i32], 16, (add S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; def SFGPR32 : RegisterClass<"ABC", [f32], 16, (add S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; ===== Instruction selection ends: ... t8: i32 = ADDrr t37, t32