Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] RFC: Indexing of structs vs arrays in getelementpointer"
2014 May 22
2
[LLVMdev] RFC: Indexing of structs vs arrays in getelementpointer
On May 22, 2014, at 3:51 PM, Chandler Carruth <chandlerc at google.com> wrote:
>
> On Thu, May 22, 2014 at 4:42 PM, Louis Gerbarg <lgg at apple.com> wrote:
> The problem that the above transform is technically illegal because “When indexing into a (optionally packed) structure, only i32 integer constants are allowed (when using a vector of indices they must all be the same
2014 May 23
2
[LLVMdev] RFC: Indexing of structs vs arrays in getelementpointer
----- Original Message -----
> From: "Chandler Carruth" <chandlerc at google.com>
> To: "Louis Gerbarg" <lgg at apple.com>
> Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>
> Sent: Thursday, May 22, 2014 7:09:49 PM
> Subject: Re: [LLVMdev] RFC: Indexing of structs vs arrays in getelementpointer
>
>
>
>
>
2007 Jun 12
3
[LLVMdev] ARM backend problem ?
Hello,
I want to compile a LLVM file into an executable running on ARM platform.
I use LLVM 2.0 with the following command lines:
llvm-as -f -o test.bc test.ll
llc -march=arm -mcpu=arm1136j-s -mattr=+v6 -f -o test.s test.bc
arm-linux-gnu-as -mcpu=arm1136j-s test.s
With the last command, I obtain the following error:
rd and rm should be different in mul
The bad instruction is
2007 Jun 12
0
[LLVMdev] ARM backend problem ?
Hi Mikael,
You are obtaining warning, not an error, right? The most arm cores,
including arm1136, can execute mul with rd = rm. So, you can ignore
this warning.
Lauro
2007/6/12, Peltier, Mikael <m-peltier at ti.com>:
>
>
>
>
> Hello,
>
>
>
> I want to compile a LLVM file into an executable running on ARM platform.
>
> I use LLVM 2.0 with the following
2010 Nov 06
2
[LLVMdev] Hoisting elements of array argument into registers
I am seeing the wf loop get optimized just fine with llvm 2.8 (and almost as good with head). I'm running on Mac OS X 10.6. I have an apple supplied llvm-gcc and a self compiled llvm 2.8. When I run
$ llvm-gcc -emit-llvm -S M.c
$ opt -O2 M.s | llvm-dis
I see that:
1. Tail recursion has been eliminated from wf
2. The accesses to sp have been promoted to registers
3. The loop has
2008 Jan 12
1
[LLVMdev] Labels
I'm attempting to modify a parser generator to emit LLVM code instead of C.
So far the experience has been trivial, but I am now running into an error
regarding labels that I can't seem to solve.
Situation 1: A label is used immediately after a void function call (l6 in
this case):
<snip>
%tmp26 = load i32* @yybegin, align 4
%tmp27 = load i32* @yyend, align 4
call void
2015 Jun 10
3
[LLVMdev] Question about NoWrap flag for SCEVAddRecExpr
I am testing vectorization on the following test case:
float x[1024], y[1024];
void myloop1() {
for (long int k = 0; k < 512; k++) {
x[2*k] = x[2*k]+y[k];
}
}
Vectorization failed due to "unsafe dependent memory operation". I traced
the LoopAccessAnalysis.cpp and found the reason is the NoWrapFlag for
SCEVAddRecExpr is not set and consequently the
2015 Jun 11
4
[LLVMdev] Question about NoWrap flag for SCEVAddRecExpr
[+Arnold]
> On Jun 10, 2015, at 1:29 PM, Sanjoy Das <sanjoy at playingwithpointers.com> wrote:
>
> [+CC Andy]
>
>> Can anyone familiar with ScalarRevolution tell me whether this is an
>> expected behavior or a bug?
>
> Assuming you're talking about 2*k, this is a bug. ScalarEvolution
> should be able to prove that {0,+,4} is <nsw> and
2013 Oct 27
2
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
The following piece of IR is a fixed point for opt -std-compile-opts/-O3:
---
target datalayout =
"e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nounwind readonly
define i32 @get32Bits(i8*
2010 Nov 07
0
[LLVMdev] Hoisting elements of array argument into registers
David Peixotto <dmp <at> rice.edu> writes:
> I am seeing the wf loop get optimized just fine with llvm 2.8 (and almost
as good with head).
I rechecked this and am I actually seeing the same results as you. I think I
must have made a stupid mistake in my tests before - sorry for the noise.
However, I found that we have a phase ordering problem which is preventing us
getting as much
2007 Jul 31
3
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
Hi,
I was talking with aKor in #llvm how we could implement custom operation
support for our ASIP architecture. We came into solution that the best
way would be to write new custom operation intrinsic and optimization
pass for raising certain type of function calls to those intrinsics
(similar to raising mallocs).
Basically our custom operation are like calls, with operand name and
multiple
2012 Dec 30
0
[LLVMdev] Cannot interchange "literal" and "identified" structs
Justin,
http://llvm.org/docs/LangRef.html#structure-type
"Identified types can be recursive, can be opaqued, and are never uniqued."
Do you think it would be less descriptive?
"Identified type, aka named llvm::StructType, is never uniqued against
other identified types nor literal types, aka unnamed StructType(s)."
?
See also;
2012 Dec 30
2
[LLVMdev] Cannot interchange "literal" and "identified" structs
With primitive types, I can interchange literal usage and type aliases in
IR:
%mytype = type i32
define void @foo(%mytype* %ptr) {
%t1 = load *%mytype** %ptr
store i32 *%t1*, *i32** %ptr
ret void
}
But for structs, I cannot:
%mytype = type { i32, i32 }
define void @foo(%mytype* %ptr) {
%t1 = load *%mytype** %ptr
store* { i32, i32 }* %t1, *{ i32, i32 }** %ptr
ret void
}
2010 Jan 29
2
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
Hey Duncan, hey everybody else,
I just stumbled upon a problem in the latest llvm-gcc trunk which is
related to my previous problem with the 64bit ABI and structs:
Given the following code:
struct float3 { float x, y, z; };
extern "C" void __attribute__((noinline)) test(float3 a, float3* res) {
res->y = a.y;
}
int main(void) {
float3 a;
float3 res;
test(a,
2012 Feb 03
5
[LLVMdev] Updating PHI for Instruction Domination?
So my best bet is to try and work in reg2mem mode and then go back to
mem2reg?
I'm curious, it seems though when you split a block that the phis get
updated, right?
On Thu, Feb 2, 2012 at 5:05 PM, Eric Christopher <echristo at apple.com> wrote:
> Not that I'm aware of.
>
> -eric
>
> On Feb 2, 2012, at 3:47 PM, Ryan Taylor wrote:
>
> So essentially I'm
2012 Feb 06
1
[LLVMdev] Fwd: Updating PHI for Instruction Domination?
---------- Forwarded message ----------
From: Ryan Taylor <ryta1203 at gmail.com>
Date: Mon, Feb 6, 2012 at 10:36 AM
Subject: Re: [LLVMdev] Updating PHI for Instruction Domination?
To: Eric Christopher <echristo at apple.com>
Since I'm not sure which instructions I might want to replicate, would it
be possible to cast the Value from "PHINode::getIncomingValue" to
2011 Jan 25
2
[LLVMdev] Update PHINode after extracting code
Hi all,
I have problem with ExtractCodeRegion (CodeExtractor.cpp).
My original program is as follows.
bb:
...
%tmp.15 = load %struct.MYSQL_ROWS** %3, align 4
...
bb1:
...
%tmp.1 = load %struct.MYSQL_ROWS** %6, align 4
...
bb4: ; preds = %bb1, %bb,
%entry
%tmp.0 = phi %struct.MYSQL_ROWS* [ null, %entry ], [ %tmp.15, %bb ], [
%tmp.1, %bb1 ]
2011 Jan 27
0
[LLVMdev] Update PHINode after extracting code
I guess I didn't have a clear question.
Suppose we have BB1 and BB2 both point to BB3.
BB1 has variable x. BB2 also as variable x.
BB3 will have PHINode for x with 2 value from BB1 and BB2.
BB1 BB2
\ /
BB3
Now if BB1 and BB2 is extracted into a function
(using ExtractCodeRegion), they will be replaced by
a basic block called codeRepl (which has a call to the extracted
2013 Jul 30
2
[LLVMdev] Eliminating PHI with Identical Inputs
Dear All,
Is there a pass (or set of passes) that will replace a phi whose input
operands all compute the same value with an instruction that computes
that value? In other words, something that will convert:
define internal i32 @function(i32 %x) {
...
bb1:
%y = add %x, 10
...
bb2:
%z = add %x, 10
...
bb3:
%phi = [bb1, %y], [bb2, %z]
into
define internal i32 @function(i32 %x) {
...
bb1:
...
2011 Jan 27
2
[LLVMdev] Update PHINode after extracting code
On 01/26/2011 07:50 PM, Vu Le wrote:
> I guess I didn't have a clear question.
>
> Suppose we have BB1 and BB2 both point to BB3.
> BB1 has variable x. BB2 also as variable x.
> BB3 will have PHINode for x with 2 value from BB1 and BB2.
> BB1 BB2
> \ /
> BB3
>
> Now if BB1 and BB2 is extracted into a function
> (using ExtractCodeRegion), they