similar to: [LLVMdev] TableGen docs

On 18 March 2014 12:54, Aaron Ballman <aaron at aaronballman.com> wrote: > Would it also make sense to include the clang usages of tablegen > somewhere in #1, and then perhaps have #2.5 about clang usages (not > volunteering you for that work btw)? Diagnostics and attributes make > heavy use of tablegen in clang, for instance. I meant to ask about this... Clang has a huge list

I'm trying to find examples of the foreach pattern being used in tablegen files. The problem I am trying to solve is to simplify the amount of tablegen code I have to produce because each operand of an instruction can be a register or a literal. So for binary, we have 4 instructions, ternary, 8, and quaternary 16 combinations. Instead of writing all the combinations out, I'd like to use

That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: multiclass instmcRegImm<...> { def rr: inst<...>; def ri: inst<...>; def ir: inst<...>; def ii: inst<...>; } multiclass instmc<...> { defm i8 : instmcRegImm<...>; ^-- repeat for 15

Hello. Are you aware of any document (preferably academic paper) describing TableGen's typing of the following fields used to describe Instruction: pattern, ins and outs. I found a few pages on TableGen, but none of them talking about these fields: http://llvm.org/docs/TableGen/LangRef.html http://llvm.org/docs/TableGen/LangIntro.html

I think a multiclass may be a better fit for what you are trying to do. In fact, this is the canonical example for multiclasses: <http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-and-instances>. --Sean Silva On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I’m trying to find examples of the foreach pattern being used in

I believe multiclasses can be nested. Could that help you reduce the duplication? --Sean Silva On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: > > multiclass

llvm/lib/Target/X86/X86InstrInfo.td: class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { .... dag OperandList = ops; string AsmString = AsmStr; } def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}">; I cannot find any document on initializing the

On 08/22/2017 03:59 AM, Alex Bradbury via llvm-dev wrote: > On 21 August 2017 at 13:23, Martin J. O'Riordan via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> But there is a downside. >> >> For each of the above I also have variations that are a result of different >> processor and ISA versions, and because of this I have to use >> ‘multiclass/defm’

On Fri, 6 May 2005, Tzu-Chien Chiu wrote: > llvm/lib/Target/X86/X86InstrInfo.td: > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > AsmStr> : Instruction { > .... > dag OperandList = ops; > string AsmString = AsmStr; > } > > def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), > "mov{l}

When I registered for dev conference, there was a field asking what I was particularly interested in learning. I didn't fill it out then , but it occurs to me now that I'd really enjoy a tutorial on how to develop a new back end. I spent some time recently reviewing existing material (documentation and code) and not making a lot of progress. Indeed, under some time pressure, I'm

The macro $src, $dest used in Instruction::AsmString must be "declared" in Instruction::OperandList, right? $$ has special meaning? On 5/6/05, Chris Lattner <sabre at nondot.org> wrote: > On Fri, 6 May 2005, Tzu-Chien Chiu wrote: > > llvm/lib/Target/X86/X86InstrInfo.td: > > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > >

I have been reading the “RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends” topic with considerable interest. This is an approach I have been considering for taming our own large instruction set, and it looks like it structures our descriptions better than the conventional approach we have used so far. However, I have another form of TableGen taming that I

Hi all, I'm sure that the last thing that you want to think about is TableGen's guts, but I'm pursuing a course in bringing TableGen up to snuff with the rest of LLVM. Basically, I would like to introduce a "TGContext" class (by analogy with LLVMContext) to harbor a proper unique'd type system and BumpPtr allocate all of TableGen's data (RecTy's, Record's,

On Oct 3, 2012, at 7:07 PM, Sean Silva <silvas at purdue.edu> wrote: > Hi all, I'm sure that the last thing that you want to think about is > TableGen's guts, but I'm pursuing a course in bringing TableGen up to > snuff with the rest of LLVM. > > Basically, I would like to introduce a "TGContext" class (by analogy > with LLVMContext) to harbor a

Yes, I understand the problem. To be more useful, TableGen would have to carry the traces along with the classes and records and (re)display the values while the substitutions are being made. I'm writing a new Programmer's Guide for TableGen and have been digging into the parse-time versus substitution-time issue. I haven't found a document that makes it clear. Can you give a quick

On Oct 3, 2012, at 7:07 PM, Sean Silva <silvas at purdue.edu> wrote: > Hi all, I'm sure that the last thing that you want to think about is > TableGen's guts, but I'm pursuing a course in bringing TableGen up to > snuff with the rest of LLVM. > > Basically, I would like to introduce a "TGContext" class (by analogy > with LLVMContext) to harbor a

Hello everyone. I apologise for the sizeable delay in sending this. The BoF was attended by quite a lot of people and there was general agreement that tablegen needs improvement in some shape of form. However there are many divergent ideas as to how to go about this improvement. Of course this is completely natural, tablegen being a versatile tool used by many different people for many different

Hello all, I have some question about usage of TableGen when adding a new LLVM Backend. There are three place to use TableGen in basic steps of document "Writing an LLVM Compiler Backend": 2. Describe the register set of the target. Use "TableGen" to generate code for register definition, register aliases, and register classes from a target-specific RegisterInfo.td input

Why do you want to eliminate dynamic_cast and exceptions from tablegen? This is just a tool run over a few thousand lines of td files. You can't measure the difference in performance if you eliminate dynamic_cast and exceptions. I think it was a huge mistake to not use RTTI and exceptions in the compiler itself but I'm sure that old horse has been beaten to death long ago. But for

Thanks for the feedback! >> Does anybody have anything else they think should go into TGContext or >> any other responsibilities it should have? Or any feedback about the >> idea in general? > > All memory allocations should go into its bump pointer, RecordKeeper should as well. Any other global state that exist should also. Sounds good. >> I'm also hoping