similar to: [LLVMdev] Question about per-operand machine model

>Resources and latency are not tied. An instruction is mapped to a scheduling class. A scheduling class is mapped to a set of resources and a per-operand list of latencies. Thanks for your kind explanation. Our heuristic algorithm have needed the latency and the resource per operand to check resource conflicts per cycle. In order to support this with LLVM, I expected a per-operand list of

Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.

On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote: > Hi Andy, > > I am trying to schedule and packetize instructions for VLIW at post-RA > stage or final codegen stage, where code transformations are not allowed > any more, because hardware can not resolve resource conflict. There is a > simple example as following: > > ADD dest_reg1, src_reg1,

On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: > Hi Andrew, > > We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models. > > To expand on what JinGu mentioned, our target has explicit ports that are used to read and

On Mar 4, 2014, at 10:05 AM, Pete Cooper <peter_cooper at apple.com> wrote: > > On Mar 3, 2014, at 2:21 PM, Andrew Trick <atrick at apple.com> wrote: > >> >> On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: >> >>> Hi Andrew, >>> >>> We are currently using a custom model where

Hi, I want to write a piece of code to instrument c++ programs. I have finished writing the pass, but I do not know how to get the resultant bitcode I ran OPT with the following arguments: opt -basiccg -basicaa -load /home/andy/llvm-3.0.src/Release/lib/InstTest.so -InstTest </home/andy/llvm-3.0.src/workspace/threadTest/Debug/threadTest.bc> -o=</home/andy/output/out.bc> /dev/null

hacker cling wrote: > Hello all, > I was playing with LLVM pass. I changed the > lib/Transforms/Hello/Hello.cpp 's content to be my own pass. Then I make > install the pass and use an example test1.c to see whether it works or > not. When I run example using the following command: > clang -emit-llvm test1.c -c -o test1.bc > opt -load

Hello all, I was playing with LLVM pass. I changed the lib/Transforms/Hello/Hello.cpp 's content to be my own pass. Then I make install the pass and use an example test1.c to see whether it works or not. When I run example using the following command: clang -emit-llvm test1.c -c -o test1.bc opt -load ../build_llvm/Debug+Asserts/lib/LLVMHello.so -hello < test1.bc > /dev/null It

I ran into an interesting problem when helping to land a scheduler .td file that my colleague had written. The problem that came up was that a multiply/add pair was not combined into an madd, but just for our CPU. Upon digging into it, the problem turned out to be that '(instregex "^SUB" ...' was matching "SUBREG_TO_REG" and incorrectly increasing the schedule length.