similar to: [LLVMdev] Debug information for outlined routine

Displaying 20 results from an estimated 6000 matches similar to: "[LLVMdev] Debug information for outlined routine"

2014 Jan 27
2
[LLVMdev] Debug information for outlined routine
----- Original Message ----- > From: "David Blaikie" <dblaikie at gmail.com> > To: "sebastien deldon (PGI)" <sebastien.deldon at pgroup.com>, "Eric Christopher" <echristo at gmail.com> > Cc: "llvmdev" <llvmdev at cs.uiuc.edu> > Sent: Monday, January 27, 2014 10:12:27 AM > Subject: Re: [LLVMdev] Debug information for
2014 Jan 27
2
[LLVMdev] Debug information for outlined routine
Yes I agree with David, I don't think we can draw analogy between lambda and outlined routines. Seb From: David Blaikie [mailto:dblaikie at gmail.com] Sent: Monday, January 27, 2014 5:51 PM To: Hal Finkel Cc: llvmdev; sebastien deldon (PGI); Eric Christopher Subject: Re: [LLVMdev] Debug information for outlined routine > Given that LLVM has no current support for outlining I don't
2013 Sep 16
2
[LLVMdev] Question about debug metadata
Hi all, What is retained type list designed for in debug metadata ? Thanks for your answer Seb ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended
2013 Oct 03
2
[LLVMdev] Setting up array ordering dwarf for arrays
Hi all, Is there a way to set up array ordering (DW_ORD_row_major or DW_ORD_col_major) using debug metadata ? Best Regards Seb ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited.
2013 Oct 03
0
[LLVMdev] Setting up array ordering dwarf for arrays
Not at the moment, we've been adding things that need additions to the metadata on an "as needed" basis. Do you have a language that allows you to swap orderings in source code? If so, then feel free to add it to the array type metadata and send a patch. -eric On Oct 3, 2013 1:15 PM, "sebastien deldon (PGI)" < sebastien.deldon at pgroup.com> wrote: > Hi all,****
2013 Sep 16
0
[LLVMdev] Question about debug metadata
It's designed to deal with types that may not be referenced via other metadata. Anonymous metadata not referenced by named metadata will be automatically removed. -eric On Mon, Sep 16, 2013 at 4:18 AM, sebastien deldon (PGI) <sebastien.deldon at pgroup.com> wrote: > Hi all, > > > > What is retained type list designed for in debug metadata ? > > > > Thanks for
2013 Oct 04
1
[LLVMdev] Setting up array ordering dwarf for arrays
Usually the array ordering is implied by the language; for example LLVM supports Fortran via Dragonegg but we still don't set the ordering explicitly, we rely on the debugger to assume the right ordering because of the language code. You wouldn't need to set ordering unless you want an ordering that isn't the language default, or you're using a language code that the debugger
2013 Feb 07
3
[LLVMdev] Is there a way to verify that debug info metadata are correct ?
Hi all, I'm using my own front-end that generates LLVM debug info metadata. I was using LLVM 2.9 debug version and I'm moving to LLVM 3.2 debug version of metadata. On my example I got llc 3.2 to fail on following assertion: llc: /work1/tools/llvm/3.2/sources/lib/CodeGen/AsmPrinter/DwarfDebug.cpp:1471: void llvm::DwarfDebug::endFunction(const llvm::MachineFunction*): Assertion `TheCU
2012 Nov 09
2
[LLVMdev] fmac generation for cortex-a9
Hi Renato, It's definitively not A15. Can this be the case that NEON units for cortex-A9 support it but isn't documented/recommended ? And as mentioned before code is working ! Seb > -----Original Message----- > From: rengolin at gmail.com [mailto:rengolin at gmail.com] On Behalf Of > Renato Golin > Sent: Friday, November 09, 2012 6:27 PM > To: Sebastien DELDON-GNB >
2012 Nov 09
2
[LLVMdev] fmac generation for cortex-a9
Hi Bastien, Weird gcc is generating fma for my platform STEricsson Novathor with Linaro, code works. It also works when I use LLVM to generate fma (using llc -mtriple=armv7-eabi). Maybe someone from ARM can answer the question ? Seb From: JF Bastien [mailto:jfb at google.com] Sent: Friday, November 09, 2012 5:36 PM To: Sebastien DELDON-GNB Cc: Anitha Boyapati; llvmdev at cs.uiuc.edu Subject:
2012 Nov 09
0
[LLVMdev] fmac generation for cortex-a9
cat /proc/cpuinfo ? Are you sure it's generating VFMA and not VMLA? On Fri, Nov 9, 2012 at 9:35 AM, Sebastien DELDON-GNB < sebastien.deldon at st.com> wrote: > Hi Renato, > > It's definitively not A15. Can this be the case that NEON units for > cortex-A9 support it but isn't documented/recommended ? > And as mentioned before code is working ! > > Seb >
2012 Nov 08
2
[LLVMdev] fmac generation for cortex-a9
Hi Anitha, Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t enable fused mac generation for me. I would like just to understand why -mtriple=armv7-eabi enables it while -mcpu=cortex-a9 seems to disable it ? Seb > -----Original Message----- > From: Anitha Boyapati [mailto:anitha.boyapati at gmail.com] > Sent: Thursday, November 08, 2012 10:22 AM > To: Sebastien
2012 Nov 09
0
[LLVMdev] fmac generation for cortex-a9
Hi Sebastien, ARMv7-M has VFMA and LLVM's "triple" is far from perfect. Wikipedia tells me NovaThor can also be A15, or STE could have cramped a VFPv4 in it? ;) Or possibly, your code never branches into the VFMA. Many things could be happening, but usually, VFMA shouldn't be generated for A9. A GCC bug, maybe? On 9 November 2012 16:51, Sebastien DELDON-GNB
2012 Jun 04
1
[LLVMdev] llc support for ARM predication ?
Hi James, Thanks for the answer, for Cortex-A9 would you recommend to generate thumb2 code or ARM code ? What would be the best performance wise ? Best Regards Seb > -----Original Message----- > From: James Molloy [mailto:james.molloy at arm.com] > Sent: Thursday, May 31, 2012 9:57 AM > To: Sebastien DELDON-GNB > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] llc support
2012 Nov 09
0
[LLVMdev] fmac generation for cortex-a9
AFAIK A9 doesn't have VFPv4 or AdvSIMDv2, so it doesn't have VFMA. I don't know what LLVM does, but it shouldn't emit VFMA when you target A9. VMLA isn't a fused multiply-add, it's a multiply followed by an add and has different latency as well as precision. On Thu, Nov 8, 2012 at 4:57 AM, Sebastien DELDON-GNB < sebastien.deldon at st.com> wrote: > Hi Anitha,
2011 Feb 28
2
[LLVMdev] Use of movupd instead of movapd for x86
Understood for the aligned case, I want to measure performance degradation for unaligned case. I mean unaligned case versus aligned. I know this is stupid, but I want to try to pass a <4 x float>* as parameter of a routine and at the call site I want to pass a misaligned pointer. Since LLVM is generating movapd instruction it will raise an exception (SEGFAULT), I just want to know if there
2012 May 30
2
[LLVMdev] llc support for ARM predication ?
Hi James, Thanks for the answer, can you elaborate on difference between thumb, thumb2, ARM, thumbv7. I'm a bit lost right now. When specifying thumbv7 llc will generate thumb only code, not thumb2 ? Best Regards Seb > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of James Molloy > Sent: Tuesday, May 29,
2013 Feb 15
2
[LLVMdev] RE : Is there any llvm neon intrinsic that maps to vmla.f32 instruction ?
Hi Lang & Renato, I eventually set up a panda board with latest linaro delivery (eabi-hf). I did some experiments using my own compiler and LLVM 3.2 as back-end. I use same flagset for my compiler (front-end) and just invoke llc with and without vmlx-forwarding attribute. So base arguments to llc are: llc -march=arm -mcpu=cortex-a9 -mattr=+neon -float-abi=hard to which I added
2012 Jul 05
3
[LLVMdev] Vector argument passing abi for ARM ?
Hi Rotem, Thanks for the quick answer, how do I know which type is legal/illegal with respect to calling convention ? Best Regards Seb > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Thursday, July 05, 2012 11:21 AM > To: Sebastien DELDON-GNB; llvmdev at cs.uiuc.edu > Subject: RE: Vector argument passing abi for ARM ? > > The
2012 Sep 21
2
[LLVMdev] RE : Question about LLVM NEON intrinsics
Hi Eli, Thanks for the answer, it clarifies the situation for me. Do you know if there is Pass in LLVM that could be adapted to 'legalize' intrinsics calls ? Or shall I define my own intrinsics for non supported types ? Best Regards Seb ________________________________________ De : Eli Friedman [eli.friedman at gmail.com] Date d'envoi : vendredi 21 septembre 2012 11:54 À : Sebastien