similar to: [LLVMdev] Why make the register list a dag for RegisterClass in target descriptor file?

On 19 January 2014 10:19, Thomson <lilotom at gmail.com> wrote: > The blow snippet in target.td shows the regList in RegisterClass is typed as > dag. Why not make it a simple list, such as list<Register>? I don't know about the original reason, but these days we have a few operators in use to make constructing those sets easier which would be much harder to do for lists.

On 08/31/2015 03:59 PM, Matthias Braun wrote: > Looks to me like the alignment is specified in tablegen. From Target.td: > > class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, > dag regList, RegAltNameIndex idx = NoRegAltName> > > X86RegisterInfo.td: > > def VR256 : RegisterClass<"X86", [v32i8,

Hi, I'm porting some existing code of mine to CVS HEAD, and don't understand something about new RegisterClass TableGen definition: class RegisterClass<string namespace, list<ValueType> regTypes,........ { ..... string Namespace = namespace; What is this "namespace" thing? It looks like it should contain the name of backend, right? // RegType

On Sat, 13 May 2006, Vladimir Prus wrote: > I'm porting some existing code of mine to CVS HEAD, and don't understand > something about new RegisterClass TableGen definition: > > class RegisterClass<string namespace, list<ValueType> regTypes,........ > { > ..... > string Namespace = namespace; > > What is this "namespace"

Looking around today, it appears that TargetRegisterClass and MCRegisterClass only includes a single alignment. This is documented as being the minimum legal alignment, but it appears to often be greater than this in practice. For instance, on x86 the alignment of %ymm0 is listed as 32, not 1. Does anyone know why this is? Additionally, where are these alignments actually defined? I

On Mar 19, 2010, at 11:04 AM, Jakob Stoklund Olesen wrote: >>> The description should only have 4 operands + variable_ops. >>> >>> How can you specify a named, variable list of output operands? >> >> Why do you need to do this? You currently can't do it. > > Because an instruction like LDM loads a variable number of registers. When it specifies

On Mar 19, 2010, at 10:28 AM, Chris Lattner wrote: > > On Mar 19, 2010, at 7:46 AM, Jakob Stoklund Olesen wrote: > >> Hi, >> >> After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like: >> >> // A list of registers separated by comma. Used by load/store multiple. >> def

Could generated assembly with option "-x86-asm-symtab=intel" be assembled by nasm directly? On Thu, Jun 21, 2012 at 2:30 PM, Sean Silva <silvas at purdue.edu> wrote: > If by "NASM format" you mean Intel syntax, then yes. In my experience most > LLVM tools refer to it with the option "-x86-asm-syntax=intel". For > example, tools/llvm-objdump has this

I saw many definitions derived from Instruction defines OutputOperandList and InputOperandList (usually in the xxxInstrFormats.td), but I don't see where they are referenced. Anything I missed here? Thanks, -Thomson -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140112/e6e87e9f/attachment.html>

Hello together, this is ma first post, so please aplogize me if post this in the wrong section. I have problem concerning ma two matrizes. After a regressione and so on, I got two matrizes Matrixres contains the results of ma calculation. Matrixr contains my detiene, which where Aldo used for the regression. Please ser the following code: #Datei einlesen residual =

I saw some LLVM generated assembly in NASM format, but did find this support in the official release. Is this supported? -- Thanks Thomson Tan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120621/c571b488/attachment.html>

I just found that some samples used link.exe from Visual Studio to generate the final image, does LLVM has a replacement for link.exe to generate the final binary? -- Thanks Thomson -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111015/1b33f012/attachment.html>

I saw there is reference to dead def on registers in LLVM source code. I am not aware of this concept from the traditional course material. What are the properties of dead def? Cheers Thomson -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150101/ea39d1e4/attachment.html>

To generate code for a target which doesn't have immediate constant as instruction operand, do I (the target specific back-end, XXXTarget) need to provide code to break up the SDNode with constant (like ISD::ADD $reg1, #1) to 2 SDNodes (ISD::LOAD $reg2, #1; ISD::ADD $reg1, $reg2) in my XXXTargetLowering::LowerOperation, or LLVM target-independent framework can do such transformation

I found that LLVM optimized the IR by replacing printf with puts. I wondered which pass did this optimization? And is it common that puts is faster (and some other metric) than printf? -- Thanks Thomson -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120617/08aa6c45/attachment.html>

Hi, After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like: // A list of registers separated by comma. Used by load/store multiple. def reglist : Operand<i32> { let PrintMethod = "printRegisterList"; } def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,

On Mar 19, 2010, at 7:46 AM, Jakob Stoklund Olesen wrote: > Hi, > > After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like: > > // A list of registers separated by comma. Used by load/store multiple. > def reglist : Operand<i32> { > let PrintMethod = "printRegisterList"; > }

On Sat, Oct 15, 2011 at 7:38 AM, Thomson <lilotom at gmail.com> wrote: > I just found that some samples used link.exe from Visual Studio to generate > the final image, does LLVM has a replacement for link.exe to generate the > final binary? > > -- > Thanks > Thomson Not currently, but a linker is being worked on. Is there any reason why link.exe is undesirable? You can

If by "NASM format" you mean Intel syntax, then yes. In my experience most LLVM tools refer to it with the option "-x86-asm-syntax=intel". For example, tools/llvm-objdump has this flag. --Sean Silva On Wed, Jun 20, 2012 at 10:12 PM, Thomson <lilotom at gmail.com> wrote: > I saw some LLVM generated assembly in NASM format, but did find this > support in the

On 9/24/2016 7:20 AM, Alex Bradbury wrote: > My concern is that all of the above adds yet more complexity to what > is already (in my view) a fairly difficult part of LLVM to understand. > The definition of MyRegisterClass is not so bad though, and perhaps it > doesn't matter how it works under the hood to the average backend > writer. I agree with the complexity, but I would