similar to: [LLVMdev] MachineInstr layer is called as what?

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] MachineInstr layer is called as what?"

2011 Feb 12
3
[PATCH] fix uncheck memory allocations
To make Btrfs code more robust, several return value checks where memory allocation can fail are introduced. I use BUG_ON where I don''t know how to handle the error properly, which increases the number of using the notorious BUG_ON, though. Signed-off-by: Yoshinori Sano <yoshinori.sano@gmail.com> --- fs/btrfs/compression.c | 6 ++++++ fs/btrfs/extent-tree.c | 2 ++
2015 Dec 03
2
Cloning a MachineInstr
> What are you trying to achieve in the end? > > — > Mehdi > > I need to insert extra NOP instructions into the bundle or at least generate a few extra ones during the assembly generation. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL:
2011 Feb 15
1
[PATCH] Btrfs: fix uncheck memory allocations
To make Btrfs code more robust, several return value checks where memory allocation can fail are introduced. I use BUG_ON where I don''t know how to handle the error properly, which increases the number of using the notorious BUG_ON, though. Signed-off-by: Yoshinori Sano <yoshinori.sano@gmail.com> --- fs/btrfs/compression.c | 6 ++++++ fs/btrfs/extent-tree.c | 4 ++++
2017 Dec 27
1
Convert MachineInstr to MCInst in AsmPrinter.cpp
Hello everyone, In the file *lib/CodeGen/AsmPrinter/AsmPrinter.cpp*, I would like to obtain an MCInst corresponding to its MachineInstr. Can anyone tell me a way to do that? If that is not possible, then, I would like to know if a given MachineInstr is an *lea *instruction and I would like to know if the symbol involved with this lea instruction is a jump-table. For instance, given a
2019 Apr 26
2
[Intel-gfx] [PATCH v2] drm: prefix header search paths with $(srctree)/
Hi Dave, > -----Original Message----- > From: Dave Airlie [mailto:airlied at gmail.com] > Sent: Friday, April 26, 2019 11:19 AM > To: Yamada, Masahiro/山田 真弘 <yamada.masahiro at socionext.com> > Cc: David Airlie <airlied at linux.ie>; Daniel Vetter <daniel at ffwll.ch>; > dri-devel <dri-devel at lists.freedesktop.org>; nouveau > <nouveau at
2012 Oct 24
0
[LLVMdev] How to Find Instruction Encoding for a MachineInstr
On 10/23/2012 1:58 PM, John Criswell wrote: > Dear All, > > I'm enhancing a MachineFunctionPass that enforces control-flow > integrity. One of the things I want to do is to set the alignment of > an instruction (by adding NOPs before it in the MachineBasicBlock or > by emitting an alignment directive to the assembler) if it causes a > specific sequence of bytes to be
2014 Jan 10
8
[LLVMdev] All backends now use the MC asm printer
In r198030 the last in tree backend was converted to use MCInst for printing assembly. I removed support for the old printer in r198959. Out of tree targets have to lower MachineInstr to MCInst to use the new printer. Cheers, Rafael
2017 May 20
2
[PATCH] drm: remove NULL pointer check for clk_disable_unprepare
After long term efforts of fixing non-common clock implementations, clk_disable() is a no-op for a NULL pointer input, and this is now tree-wide consistent. All clock consumers can safely call clk_disable(_unprepare) without NULL pointer check. Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com> --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 15 +++++----------
2012 Oct 23
4
[LLVMdev] How to Find Instruction Encoding for a MachineInstr
Dear All, I'm enhancing a MachineFunctionPass that enforces control-flow integrity. One of the things I want to do is to set the alignment of an instruction (by adding NOPs before it in the MachineBasicBlock or by emitting an alignment directive to the assembler) if it causes a specific sequence of bytes to be generated at a specific alignment. The goal is to ensure that sequences of
2019 Apr 26
1
[PATCH v2] drm: prefix header search paths with $(srctree)/
Hi. On Fri, Mar 29, 2019 at 8:37 PM Masahiro Yamada <yamada.masahiro at socionext.com> wrote: > > Currently, the Kbuild core manipulates header search paths in a crazy > way [1]. > > To fix this mess, I want all Makefiles to add explicit $(srctree)/ to > the search paths in the srctree. Some Makefiles are already written in > that way, but not all. The goal of this
2019 Mar 29
4
[PATCH v2] drm: prefix header search paths with $(srctree)/
Currently, the Kbuild core manipulates header search paths in a crazy way [1]. To fix this mess, I want all Makefiles to add explicit $(srctree)/ to the search paths in the srctree. Some Makefiles are already written in that way, but not all. The goal of this work is to make the notation consistent, and finally get rid of the gross hacks. Having whitespaces after -I does not matter since commit
2012 Oct 24
1
[LLVMdev] How to Find Instruction Encoding for a MachineInstr
On Oct 23, 2012, at 6:22 PM, Joshua Cranmer <pidgeot18 at gmail.com> wrote: > On 10/23/2012 1:58 PM, John Criswell wrote: >> Dear All, >> >> I'm enhancing a MachineFunctionPass that enforces control-flow integrity. One of the things I want to do is to set the alignment of an instruction (by adding NOPs before it in the MachineBasicBlock or by emitting an alignment
2019 Jan 31
2
[PATCH] drm: prefix header search paths with $(srctree)/
Currently, the Kbuild core manipulates header search paths in a crazy way [1]. To fix this mess, I want all Makefiles to add explicit $(srctree)/ to the search paths in the srctree. Some Makefiles are already written in that way, but not all. The goal of this work is to make the notation consistent, and finally get rid of the gross hacks. Having whitespaces after -I does not matter since commit
2018 Apr 17
0
How to create and insert a call MachineInstr?
Hi Tim, I'm sorry to bother you again. Since I have met the problem, how to check used registers and avoid clobbering live registers, which you mentioned in the email. I am working in the function X86InstrInfo::storeRegToStackSlot, which is in lib/Target/X86/X86InstrInfo.cpp. And I have an extra problem, may I use MOV64mr and two addReg to set two registers as its arguments? I want to use
2018 Dec 17
3
[PATCH v3 00/12] x86, kbuild: revert macrofying inline assembly code
This series reverts the in-kernel workarounds for inlining issues. The commit description of 77b0bf55bc67 mentioned "We also hope that GCC will eventually get fixed,..." Now, GCC provides a solution. https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html explains the new "asm inline" syntax. The performance issue will be eventually solved. [About Code cleanups] I know Nadam
2018 Dec 17
3
[PATCH v3 00/12] x86, kbuild: revert macrofying inline assembly code
This series reverts the in-kernel workarounds for inlining issues. The commit description of 77b0bf55bc67 mentioned "We also hope that GCC will eventually get fixed,..." Now, GCC provides a solution. https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html explains the new "asm inline" syntax. The performance issue will be eventually solved. [About Code cleanups] I know Nadam
2018 Apr 13
2
How to create and insert a call MachineInstr?
Thanks for your help! I'm much more clear about this problem. Will 2018-04-13 17:53 GMT+08:00 Tim Northover <t.p.northover at gmail.com>: > Hi Will, > > On 13 April 2018 at 09:50, Will Lester via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > I have used BuildMI to build a MachineInstr. But it seems that a call > > MachineInstr only has one parameter
2018 Sep 28
3
error: expected memory with 32-bit signed offset
Hi, I want to encode Loongson ISA initially https://gist.github.com/xiangzhai/8ae6966e2f02a94e180dd16ff1cd60ac gslbx           $2,0($3,$4) It is equivalent to: dadd $1, $3, $4 lb $2,0($1) I just use  mem_simmptr  as the default value of  DAGOperand MO , because  MipsMemAsmOperand  use  parseMemOperand  to parse general  MemOffset  and only *one*  AnyRegister , for example: 0($1) But 
2009 Jul 10
2
[LLVMdev] MCInst
Can someone explain what MCInst is vs. MachineIntr? I'm porting some patches we have here that affect MachineInstrs and am wondering whether I need to make similar changes in MCInst. Why do we have two machine instruction representations? -Dave
2014 Mar 12
2
[LLVMdev] Hazard recognition using MCInst
Dear All, I am following a flow to generate object files(.o) from input (.s assembly) files. The input .s is given to AsmParser, which creates MCInst after matching instruction opcode. These MCInst are converted to MCStream and then finally emitting to an object file using Target Code Emitter. I am considering whether hazard recognition can be done on the list of MCInst, which I get after