similar to: [LLVMdev] All backends now use the MC asm printer

Hello, When I run LLC with option "-O0 -march=sparc" on following testcase, fast register allocator crashes with "UNREACHABLE executed" error. LLC generates code successfully with other standard register allocators available. $ cat call.ll define void @test() nounwind { entry: %0 = tail call i32 (...)* @foo() nounwind tail call void (...)* @bar() nounwind ret void }

On Jan 7, 2011, at 2:36 PM, Venkatraman Govindaraju wrote: > When I run LLC with option "-O0 -march=sparc" on following testcase, > fast register allocator crashes with "UNREACHABLE executed" error. LLC > generates code successfully with other standard register allocators > available. I haven't investigated the Sparc backend specifically but... My guess is

Hi all, In RISC-V ISA, the range of conditional branches is within 4KiB. In current implementation, if the branch target is out of range, LLVM MC will issue an error message to tell users it could not resolve the fixup record. I have compared the result with the GNU assembler. GNU assembler will convert the branch to inverted one plus jump to make the branch possible. The range of unconditional

Hello, I'm interested in the status of LLVM-MC. My particular interest is in generating executables for ARM embedded applications. I assume this application is not terribly high on the priority list, so I would like to know how I can contribute. Can someone point me to some information and/or docs on the project and its status. Also, if someone could give me an example of how

On 10 May 2018 at 21:58, Andrew Trick <atrick at apple.com> wrote: > Fantastic writeup! It’s great to see so much progress on fundamental > infrastructure. > > My time for LLVM code review is extremely limited. Can someone work with > Andrea to get these patches in? Hi Andrew, Same here, but this has been a long goal for me, too, so I'll do my best. -- cheers,

On Mar 5, 2010, at 3:20 PM, Wayne Anderson wrote: > Hello, > > I'm interested in the status of LLVM-MC. My particular interest is in > generating executables for ARM embedded applications. I assume this > application is not terribly high on the priority list, so I would like > to know how I can contribute. Can someone point me to some > information and/or

This sounds very similar to what PowerPC does, see: https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp However, PowerPC is doing this in the compiler backend, not in the assembler. One issue is that the process must be iterative, because branches can go both forward and backward, and replacing some branch instructions with the branch pairs can then

Hi All, A self-follow up and rephrase of my previous question with updated subject: What I want to do is to analyze hand-written assembly code with 'full details' where semantics of each instruction can be known in LLVM passes. Many of such instructions have no corresponding counterparts in IR/MIR forms, such as 'syscall' 'iret', etc. At MC level, such assembly code can

Hello, I have some questions regarding folding operations with symbols during the instruction print stage with MC. At the moment I'm working with global symbols but i guess that other symbol types should be equivalent. My first question is how can i negate the address of a symbol? Consider this piece of code: char g_var[80]; char foo(int a) { return g_var[a]; } this gets compiles into

Hi Jim, Thanks for reply. I'm sorry I didn't make myself clear enough. The MCInst created by MCDisassembler depends on the instructions defined in td files. These instructions do not have a one to one mapping to ARM instructions. There are usually one or more instructions defined in the td file correspond to one actual ARM instruction. Thanks, David On Thu, Jun 7, 2012 at 1:27 PM, Jim

That depends on how you define "one ARM instruction." It's not a clear cut thing. For example, is "add r1, r2, r3" the same ARM instruction as "add r1, r2, #4"? What is a distinct instruction and what's a variant encoding of the same instruction is often entirely a matter of convenience. -Jim On Jun 8, 2012, at 6:40 AM, Fan Dawei <fandawei.s at

On Tue, 2014-01-14 at 22:59 -0800, Craig Topper wrote: > I started trying to fix this tonight but it's pretty nasty to fix. > I'll try to make another go at it later this week. Much of it seems fixed already; what's left to fix? The segment prefix override? Does that mean we get to fix disassembly of '0x65 0xa4' while we're at it? (Although we can't even

Hello, I am working on backend development and would like to utilize my target's MCAsmParser inside of an MCInst-level class implementation. I noticed that the AsmParser is registered with the target registry however I am having no luck grepping for a "template" of how to instantiate it and have yet to find specific documentation on how it is done. Any ideas or help is greatly

On Jun 7, 2012, at 7:53 AM, Fan Dawei <fandawei.s at gmail.com> wrote: > Hi Tim, > > Thanks a lot for your help! I'm very grateful. > > libc.so is a prelinked library, I'll build a non-prelinked one and have another try. > > I'm now at the start of a binary translation project. I want to convert ARM binary code [*] to llvm ir, which is then translated to

Hi Tim, Thanks a lot for your help! I'm very grateful. libc.so is a prelinked library, I'll build a non-prelinked one and have another try. I'm now at the start of a binary translation project. I want to convert ARM binary code [*] to llvm ir, which is then translated to binary for our mips like architecture. That's why I'm looking for a decoder for ARM binary. The

Thanks Andrew and Renato, One think I didn't mention, and I should probably made it more explicit in my RFC is that: "the new predicate framework is extensible". That means, developers can extend it by adding new Check predicates. As long as they also teach the PredicateExpander how to do the lowering for those new predicates, then everything should be fine. -- In the RFC I

I'm in the process of evaluating whether to make the PTX assembly printer MC-aware. It appears that most other back-ends have made the switch, but I want to evaluate if it makes sense for the PTX back-end. First, PTX is a text-only format; there are no instruction encodings or object files. Second, the PTX back-end will never tie into the JIT compiler. After experimenting with the

I have been reading the BLOG about the LLVM MC Project and have a number of queries about ARM support. 1) When is it anticipated that the ARM assembler will reach production quality? 2) Is the complete ARMv7 ISA supported? 3) Is the syntax used by the ARM assembler/disassembler that used by GAS or are there incompatibilities? 4) What is the current state of the ARM instruction parser and

Instead of just upcasing them, can we add prefix ARCH_? --Venkatraman On Tue, Aug 25, 2009 at 2:36 AM, Eric Christopher<echristo at apple.com> wrote: > > On Aug 25, 2009, at 12:32 AM, Daniel Dunbar wrote: > >> Hi, >> >> I think I should rename the constants to be a little less likely to >> collide. I think just upcasing them might be good enough? > >

> On May 11, 2018, at 4:26 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > The goal is to help users defining a predicate the check logic. If we use a TIIPredicate, we specify the logic only once, in a declarative way, and then we let tablegen generate code for us. > > If for some reason, a user doesn't want to use this approach, then they can still