similar to: [LLVMdev] Specify the default target when configuring LLVM

Martin hi. It seems like you have in fact understood the offered solution, and its disadvantages. The thing is, that as far as I understand Tblgen (and I think I do :-) ), The idea behind it is that records only have state (i.e., fields), and not a behavior (i.e., methods) - so dynamic evaluation can only be achieved by built-in functions. (e.g., !if(), !foreach() etc...). Maybe you can try

Thanks again Elior, Yes, I tried using '!if', etc. but I just get type mismatches for the initializer (int) - probably something daft I'm doing :-( MartinO -----Original Message----- From: Malul, Elior [mailto:elior.malul at intel.com] Sent: 29 September 2013 09:19 To: Martin.ORiordan at movidius.com; llvmdev at cs.uiuc.edu Subject: RE: [LLVMdev] Tblgen and computed expressions

Thanks Elior, Sorry for the delay - emergencies never seem to go away in compiler development ;-) That sounds like an interesting approach, a kind-of pre-processor for TD files. But will this still not result in a constant, although externally provided, or have I misunderstood? What I would like to do is compute a different value depending on which '-target-cpu <cpu>' option was

Hi, I have bitcode files built by LLVM v3.3 and need to process them using v3.4 tools. While I don't expect a lot of backward compatibility in LLVM, luckily it seems everything's working fine, except for reading source line information attached to instructions. I use this piece of code [0] to get source line information. For v3.4, instruction.getMetadata returns NULL. I used llvm-dis to

Thanks Eric, but could you give me a little bit more hints or pointers please? I looked into DebugInfo.h, but I'm still not sure how to start. It sounds like I'd have to somehow manually extract metadata nodes from an instruction. Thanks, JS On Wed, Jan 22, 2014 at 10:14 PM, Eric Christopher <echristo at gmail.com>wrote: > This is likely going to be difficult if possible. I

On Apr 26, 2013, at 3:53 AM, Martin J. O'Riordan <Martin.ORiordan at movidius.com> wrote: > I am migrating the llvm/clang derived compiler for our processor from the > v3.1 to v3.2 codebase. This has mostly gone well except that instruction > latency scheduling is no longer happening. > > The people who implemented this previously sub-classed 'ScheduleDAGInstrs'

Hi LLVMDev, I am revising an existing LLVM backend for a new variant of our CPU architecture. I have looked at other targets, and the approach used by Hexagon seems to suit most of my needs quite well, so I am using Predicates to enable/disable instructions for the architectures. This works very well for disabling old instructions, and enabling new instructions. For the remaining instructions

Martin hi. I encountered a similar problem, and made a solution for it. The solution is a tblgen enhancement, and enables tblgen code expressions to be dynamically evaluated. It works as follows: 1. Code expressions have 'special runtime evaluation' expression (very similar to strings in ruby), e.g.: code c = {[ My name is #{injected}. }. 2. I have added another command line switch for

Hello, Please consider including upstream commit 08e34eb14fe4cfd934b5c169a7682a969457c4ea in the next v3.2.y release. It was included upstream as of v3.3-rc1. It has been tested and confirmed to resolve http://bugs.launchpad.net/bugs/1154608 . commit 08e34eb14fe4cfd934b5c169a7682a969457c4ea Author: Laszlo Ersek <lersek at redhat.com> Date: Sun Dec 11 01:48:59 2011 +0000

Hello, Please consider including upstream commit 08e34eb14fe4cfd934b5c169a7682a969457c4ea in the next v3.2.y release. It was included upstream as of v3.3-rc1. It has been tested and confirmed to resolve http://bugs.launchpad.net/bugs/1154608 . commit 08e34eb14fe4cfd934b5c169a7682a969457c4ea Author: Laszlo Ersek <lersek at redhat.com> Date: Sun Dec 11 01:48:59 2011 +0000

Our out-of-tree LLVM compiler is configured and built on Linux, but I cannot get it to run under the Windows 10 Linux Subsystem. When run in this context it reports a crash: warning: Error disabling address space randomisation: Success warning: linux_ptrace_test_ret_to_nx: PTRACE_KILL waitpid returned -1: Interrupted system call Program received signal SIGSEGV, Segmentation fault.

Hi LLVM-Devs, When I try to configure LLVM v6.0 RC2 (SVN Rev #324869) on Windows (I haven't yet had a chance to try on Linux), I get a series of errors such as this: CMake Error at cmake/modules/AddLLVM.cmake:1333 (add_dependencies): The dependency target "(" of target "check-all" does not exist. Call Stack (most recent call first): CMakeLists.txt:937

Maybe it's caused by the space after the X86 argument? Can you try removing all the -D flags, and see if that works? Then add them one by one to see which is the culprit? -Dimitry > On 17 Feb 2018, at 23:11, Martin J. O'Riordan via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi LLVM-Devs, > > When I try to configure LLVM v6.0 RC2 (SVN Rev #324869) on Windows

Dear all, in order to estimate transition-specific probabilities in a multi-state model i applied the 'probtrans()' function from the 'mstate'-package. Now, i am at loss with the following message (see attached example): Warning message: In probtrans(msf.0, predt = 0) : Negative diagonal elements of (I+dA); the estimate may not be meaningful. I am not very familiar with matrix

Thanks again for your help Steve, I’m thinking perhaps my “SelectADDRrr” pattern is inadequate. The sign-extension is at the hardware level, the code generator sees (should see) it as a 16-bit signed register value. My implementation is just: bool SHAVEISelDAGtoDAG::SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset) { if ((Addr.getOpcode() == ISD::ADD) { Base

I've no idea, but without it, the 'std::to_string' definitions are not enabled! -----Original Message----- From: Renato Golin [mailto:renato.golin at linaro.org] Sent: 06 July 2016 19:35 To: Martin.ORiordan at movidius.com Cc: LLVM Developers <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] GCC prerequisites for building LLVM head? On 6 July 2016 at 19:02, Martin J.

We discovered what is happening. SDAGCombiner essentially looks at various combinations of nodes to do with vectors, and when it can, it creates a vector shuffle. The problem is, that our vector shuffle lowering builds new trees with vector element, or vector sub-vector insert sequences. The generic DAGCombiner, reconstructs these into a new shuffle, and so the loop continues - we reduce it,

Thanks :) From: 陳韋任 [mailto:chenwj.cs97g at g2.nctu.edu.tw] Sent: 14 April 2017 12:53 To: Martin J. O'Riordan <martin.oriordan at movidius.com> Cc: LLVM Developers <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] Options for timing passes in LLVM? Refer to `llc` document [1], it would be `--time-passes`. [1] http://llvm.org/docs/CommandGuide/llc.html HTH,

I was investigating an error diagnostic in the following test example: typedef signed char char16 __attribute__((ext_vector_type(16))); void test( char16 srcA, char16 srcB, char16 *dst) { *dst = ( srcA == srcB ); } which produces the message: mismatch.c:5:10: error: assigning to 'char16' from incompatible type 'char __attribute__((ext_vector_type(16)))' *dst = (

Thanks Ahmed and also Alex for your replies. This is more or less what I was realising, but it is a great confidence booster to know that it is the correct way also. I can replace all of my various 'Select*' specialisations with version that use 'ReplaceNode/SelectCode' and return 'void', but what about the places where I currently call 'Select(N)' directly?