similar to: [LLVMdev] Question about Pre-RA-schedule in LLVM3.3

At 2013-12-15 22:43:34,"Caldarale, Charles R" <Chuck.Caldarale at unisys.com> wrote: >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] >> On Behalf Of Haishan >> Subject: [LLVMdev] Question about Pre-RA-schedule in LLVM3.3 > >> My clang version is 3.3 and debug build. > >> //test.c >> int a[6] = {1, 2, 3, 4, 5,

> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Haishan > Subject: [LLVMdev] Question about Pre-RA-schedule in LLVM3.3 > My clang version is 3.3 and debug build. > //test.c > int a[6] = {1, 2, 3, 4, 5, 6} > int main() { >  a[0] = a[5]; >  a[1] = a[4]; >  a[2] = a[5]; > } > //end test.c > Then test.dump is

The flag -enable-aa-sched-mi should do what you want you want in the MachineScheduler pass. If you want to do it in the selection DAG, there is a subtarget hook that might do it: TargetSubtargetInfo::useAA() LLVM won’t generate the schedule you want anyway for Intel core processors, but the alias analysis can be useful in general. -Andy On Dec 16, 2013, at 6:03 AM, Haishan <hndxvon at

Hi all, I think I've managed to trick the legacy MemCpyOpt (MCO) into an incorrect transform, but I would like to confirm the validity of my counterexample before working on the fix. Suppose the following IR: %T = type { i32, i32 } define void @f(%T* %a, %T* %b, %T* %c, %T* %d) { %val = load %T, %T* %a, !alias.scope !{!10} ; store1 ; Aliases the load

In http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20120827/063200.html, consecutive bitfields are wrapped as a group and represented as a large integer and emits loads stores and bit operations appropriate for extracting bits from within it. It fixes the problem of violating C++11 memory model that original widen load/store of bitfield was facing. It also brings more coalescing

On Thu, Mar 9, 2017 at 10:54 AM, Hal Finkel <hfinkel at anl.gov> wrote: > On 03/09/2017 12:14 PM, Wei Mi via llvm-dev wrote: >> >> In >> http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20120827/063200.html, >> consecutive bitfields are wrapped as a group and represented as a >> large integer and emits loads stores and bit operations appropriate

Hi, I have a problem with making PCA plots that are readable. I would like to set different sympols instead of the numbers of my samples or their names, that I get plotted (xlabs). How is this possible? With points, i don´t seem to get the right data plotted onto the PCA plot, as I do not quite understand from where it is taken. I dont know how to plot the correct columns of the prcomp

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, I have been using rsync to backup our primary data stores. It works fine. Here are the options I use for doing that: rsync --recursive --links --times --dirs --stats --delete \ --itemize-changes --quiet --exclude-from=exclude-filename \ /data-store1/ /data-store2/ Recently I have had the need to actually synchronize the files between

On 03/09/2017 12:28 PM, Krzysztof Parzyszek via llvm-dev wrote: > We could add intrinsics to extract/insert a bitfield, which would > simplify a lot of that bitwise logic. But then you need to teach a bunch of places about how to simply them, fold using bitwise logic and other things that reduce demanded bits into them, etc. This seems like a difficult tradeoff. -Hal > >

Hi All, Using clang+llvm at head, I noticed a weird behaviour with the following reduced testcase : $ cat test.c #include <stdint.h> struct R { uint16_t a; uint16_t b; }; volatile struct R * const addr = (volatile struct R *) 416; void test(uint16_t a) { struct R r = { a, 1 }; *addr = r; } $ clang -O2 -o - -emit-llvm -S -c test.c ; ModuleID = 'test.c' target

Hi All, In the language reference manual, the access behavior of the memcpy, memmove and memset intrinsics is not well defined with respect to the volatile flag. The LRM even states that "it is unwise to depend on it". This forces optimization passes to be conservatively correct and prevent optimizations. A very simple example of this is : $ cat test.c #include <stdint.h>

Hi, Thanks for your answer. I am looking for a map, and the data structure of this map is map<const Instruction *, vector<MachineInstr*> > In this map, its keyvalue is IR instruction pointer, and its second value is a container which is composed of MachineInstr lowering by its keyvalue. For example: IR Instruction %0 = load i32* getelementptr inbounds ([6 x i32]* @a, i32 0,

As a results of my investigations, the thread is also added to cfe-dev. The context : while porting my company code from the LLVM/Clang releases 3.1 to 3.2, I stumbled on a code size and performance regression. The testcase is : $ cat test.c #include <stdint.h> struct R { uint16_t a; uint16_t b; }; volatile struct R * const addr = (volatile struct R *) 416; void test(uint16_t a) {

Hi, The LLVM coding style does not specify anything about the use of signed/unsigned integer, and the codebase is inconsistent (there is a majority of code that is using unsigned index in loops today though). I'd like to suggest that we specify to prefer `int` when possible and use `unsigned` only for bitmask and when you intend to rely on wrapping behavior, see:

I doubt you needed to add cfe-dev here. Sorry I hadn't seen this, this seems like an easy and simple deficiency in the IR intrinsic for memcpy. See below. On Sun, Jan 20, 2013 at 1:42 PM, Arnaud de Grandmaison < arnaud.allarddegrandmaison at parrot.com> wrote: > define void @test(i16 zeroext %a) nounwind uwtable { > %r.sroa.0 = alloca i16, align 2 > %r.sroa.1 = alloca i16,

I can't think of a better way to do this, so I think it's ok. I also submitted a complementary patch on llvm-commits clarifying volatile semantics. -Andy On Jan 28, 2013, at 8:54 AM, Arnaud A. de Grandmaison <arnaud.allarddegrandmaison at parrot.com> wrote: > Hi All, > > In the language reference manual, the access behavior of the memcpy, > memmove and memset

Hey, I have two identical machines setup with a RAID 5 array. One of them is used for failovers and data from the master is synced everyday using rsync to the failover machine. The data on this disks are usually intranet KB's, DB's etc.. The RAID 5 arrays are formatted using the default options i,e mkfs.ext3 /dev/Xda. The RAID controller is 3ware escalade and each disk member in the RAID

Hello. I have problem as below: Nov 8 10:41:52 store1 dovecot: auth: Debug: auth(master at example.com,::1,master,</qEuMafqyAAAAAAAAAAAAAAAAAAAAAAB>): Master user lookup for login: jkrzyz at example.com Nov 8 10:41:52 store1 dovecot: auth: Debug: passwd-file(master at example.com,::1,master,</qEuMafqyAAAAAAAAAAAAAAAAAAAAAAB>): lookup: user=master at example.com

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I made the switch to llvm3.3, and encountered a flt_rounds I'm using a soft float architecture and hopefully people have some ideas on how to help: I received: i32 = flt_rounds "Do not know how to promote this operator!" I currently do not have any custom setting for the FLT_ROUNDS_ I'd like to just replace the FLT_ROUNDS_ with a "1" value. Any thoughts on how