similar to: [LLVMdev] How to build a map between IR Instruction and MachineInstrs?

Hi, Thanks for your answer. I am looking for a map, and the data structure of this map is map<const Instruction *, vector<MachineInstr*> > In this map, its keyvalue is IR instruction pointer, and its second value is a container which is composed of MachineInstr lowering by its keyvalue. For example: IR Instruction %0 = load i32* getelementptr inbounds ([6 x i32]* @a, i32 0,

Hi, I have implemented a pair intrinsic nodes in back-end, But there is a chain dependence between two intrinsic nodes. So in the Pre-RA-sched stage, these two intrinsic nodes would be apart. I expect that there is no node between these two intrinsic nodes, therefore, I guess it would be work if there is a MVT::Glue between these nodes. But I don’t know how to add. Thanks in advance. Haishan

At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level

On Jan 3, 2014, at 1:06 PM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 3, 2014, at 12:10 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > >> >> On Jan 3, 2014, at 11:01 AM, Andrew Trick <atrick at apple.com> wrote: >> >>> >>> On Jan 3, 2014, at 4:58 AM, Haishan <hndxvon at 163.com> wrote: >>>

On Jan 3, 2014, at 11:01 AM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 3, 2014, at 4:58 AM, Haishan <hndxvon at 163.com> wrote: > >> >> At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: >> >> On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: >> My update steps are shown

The flag -enable-aa-sched-mi should do what you want you want in the MachineScheduler pass. If you want to do it in the selection DAG, there is a subtarget hook that might do it: TargetSubtargetInfo::useAA() LLVM won’t generate the schedule you want anyway for Intel core processors, but the alias analysis can be useful in general. -Andy On Dec 16, 2013, at 6:03 AM, Haishan <hndxvon at

At 2013-12-15 22:43:34,"Caldarale, Charles R" <Chuck.Caldarale at unisys.com> wrote: >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] >> On Behalf Of Haishan >> Subject: [LLVMdev] Question about Pre-RA-schedule in LLVM3.3 > >> My clang version is 3.3 and debug build. > >> //test.c >> int a[6] = {1, 2, 3, 4, 5,

On Jan 4, 2014, at 4:38 AM, Haishan <hndxvon at 163.com> wrote: > At 2014-01-04 06:11:38,"Jakob Stoklund Olesen" <stoklund at 2pi.dk> wrote: > > On Jan 3, 2014, at 1:52 PM, Andrew Trick <atrick at apple.com> wrote: > >> He really just wants to rerun LiveIntervals analysis, but LiveVariables is no longer available. Would it work just to clear all

Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probable reason of this error is that no LiveInterval information for newly MBB which is used by Register Allocation. And, LiveIntervals depend

Are these known to be broken right now? I get failure when using either. $ llc -march=arm -print-machineinstrs hw.bc ... BB#0: derived from LLVM BB %entry Live Ins: %LR %R7 %SP<def> = SUBri %SP<kill>, 8, 14, %reg0, %reg0 STR %LR<kill>, %SP, %reg0, 4, 14, %reg0; mem:ST4[0 llc 0x008b3304 PrintStackTrace(void*) + 45 1 llc 0x008b390c

On Tue, Apr 30, 2013 at 12:48 AM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com> wrote: > Hi,**** > > ** ** > > We’ve recently encountered a problem in our compiler where the line number > in debug info jumps back and force even at O0. This is caused by DAG node > ordering not being properly kept during legalization and instruction > selection. There are still uncaught cases

On Apr 30, 2013, at 11:00 AM, "Guo, Xiaoyi" <Xiaoyi.Guo at amd.com> wrote: > Hi Eric, > > Sorry I wasn’t clear. The problem happened in the “source” pre-RA scheduler, which relies on DAG node ordering to schedule the nodes. In your case, Eric's suggestion was effectively "start implementing fast-isel". Which is not a bad idea if you want to reduce compile

Hi Eric, Sorry I wasn't clear. The problem happened in the "source" pre-RA scheduler, which relies on DAG node ordering to schedule the nodes. Xiaoyi From: Eric Christopher [mailto:echristo at gmail.com] Sent: Tuesday, April 30, 2013 12:54 AM To: Guo, Xiaoyi Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] [PATCH] Propagate DAG node ordering during legalization and

> Are these known to be broken right now? I get failure when using either. > > $ llc -march=arm -print-machineinstrs hw.bc Seems due to David's patches. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

On Friday 13 November 2009 15:17, Anton Korobeynikov wrote: > > Are these known to be broken right now? I get failure when using either. > > > > $ llc -march=arm -print-machineinstrs hw.bc > > Seems due to David's patches. Ok. Send me a testcase and I will fix. This should be put into the testbase. -Dave

On Nov 13, 2009, at 1:49 PM, David Greene wrote: > On Friday 13 November 2009 15:17, you wrote: >>> Are these known to be broken right now? I get failure when using either. >>> >>> $ llc -march=arm -print-machineinstrs hw.bc >> >> Seems due to David's patches. > > Ok, it's faulting in SlotTracker with what looks like a bad Function. One

Hi, We've recently encountered a problem in our compiler where the line number in debug info jumps back and force even at O0. This is caused by DAG node ordering not being properly kept during legalization and instruction selection. There are still uncaught cases after applying the patch mentioned here. So I have decided to implement the approach suggested by Andy as below. i.e. maintain the

On Friday 13 November 2009 16:28, Dan Gohman wrote: > On Nov 13, 2009, at 1:49 PM, David Greene wrote: > > On Friday 13 November 2009 15:17, you wrote: > >>> Are these known to be broken right now? I get failure when using > >>> either. > >>> > >>> $ llc -march=arm -print-machineinstrs hw.bc > >> > >> Seems due to

On Friday 13 November 2009 15:17, you wrote: > > Are these known to be broken right now? I get failure when using either. > > > > $ llc -march=arm -print-machineinstrs hw.bc > > Seems due to David's patches. Ok, it's faulting in SlotTracker with what looks like a bad Function. One of the Argument values is corrupted. I'm not abdicating responsibility, but at

Updating the subject line. From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Gautam Chakrabarti via llvm-dev Sent: Wednesday, March 28, 2018 11:58 PM To: LLVM Dev <llvm-dev at lists.llvm.org> Subject: [llvm-dev] Why do constant SD nodes not set the IROrder? Specifically I would like to understand why ConstantSDNode and ConstantFPSDNode do not set the IR ordering like