similar to: [LLVMdev] Support for delayed constants in ARM integrated assembler

In an earlier email[1] I proposed adding support for the ldr pseud-instruction to the ARM integrated assembler. After some discussion the overall consensus seemed to be that it was worth adding. One concern was that we needed to have adequate testing. I promised to provide more details on what the behavior should be and provide some tests before starting the implementation. The FileCheck-ified

From: Jim Grosbach [mailto:grosbach at apple.com] Sent: Friday, October 25, 2013 4:31 PM To: David Peixotto Cc: Renato Golin; LLVM Dev Subject: Re: [LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> wrote: Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below.

Moving discussion to llvm-commits now that I have a more developed implementation: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20131111/195401. html > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of David Peixotto > Sent: Tuesday, November 12, 2013 11:09 AM > To: 'Amara Emerson' >

Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From: Renato Golin [mailto:renato.golin at linaro.org] Sent: Friday, October 25, 2013 1:11 PM To: David Peixotto Cc: LLVM Dev; Logan Chien; Gabor Ballabas; Rafael Espíndola; Richard Barton; Amara Emerson Subject:

On Oct 25, 2013, at 6:14 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: Friday, October 25, 2013 4:31 PM > To: David Peixotto > Cc: Renato Golin; LLVM Dev > Subject: Re: [LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler > > > On Oct 25, 2013, at 3:53 PM, David Peixotto

On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. > > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > > > From: Renato Golin [mailto:renato.golin at linaro.org] > Sent: Friday, October 25, 2013 1:11 PM

Both armasm and gnu as support an ldr pseudo instruction for loading constants that lowers to either a mov, movn, or a pc-relative ldr from the constant pool. It would be great if the llvm integrated assembler could support this feature as well. For example, using gnu as to compile this code: .text foo: ldr r0, =0x1 ldr r0, =-0x1 ldr r0, =0x1000001 ldr r0, =bar

On 25 October 2013 18:33, David Peixotto <dpeixott at codeaurora.org> wrote: > Both armasm and gnu as support an ldr pseudo instruction for loading > constants that lowers to either a mov, movn, or a pc-relative ldr from the > constant pool. It would be great if the llvm integrated assembler could > support this feature as well. > Hi David, As much as I think that it's

> > I was thinking that without the .ltorg directive the constant pool > > would go at the end of the section. > > > So where does the assembler place the constant pool(s) if that directive > isn't present? I was under the impression it was always required. >From my understanding it is not required. I see that GCC will place it at the end of the section. I don't

Hi David, Thanks for your efforts here. I have a few comments on your patch, although I realise it's still a work in progress. +class ConstantPool { + MCSymbol *Label; + typedef std::vector<const MCExpr*> EntryVecTy; Use a SmallVector here? + MCSymbol *getLabel() {return Label;} + size_t getNumEntries() {return Entries.size();} + const MCExpr *getEntry(size_t Num) {return

> > I wrote the tests before I did the actual implementation and I thought > > I would be generating the relocations myself. The implementation > > turned out to be much simpler than I imagined and I was able to lean > > on the existing support for generating relocations and fixups. I > > expect all these relocations would be covered by other tests. > > >

On Nov 1, 2013, at 12:06 PM, David Peixotto <dpeixott at codeaurora.org> wrote: >>> I was thinking that without the .ltorg directive the constant pool >>> would go at the end of the section. >>> >> So where does the assembler place the constant pool(s) if that directive >> isn't present? I was under the impression it was always required. >

Hi Amara, Thanks for your suggestions. I have made the changes you suggested and added a new test to check that we print an error when parsing a non-ldr mnemonic with an operand containing `=`. The updated patch is attached. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > -----Original Message----- > From: Amara Emerson

> Also what is the preferred method for MC way of setting out subsection > sizes after the fact? I am guessing I need to use an MCFixup? > How do I get an MCExpr to evaluate a method for the subsection size? > Is there an equivalent use in the places using MCFixup? > Do I need to add a new subclass to MCExpr for doing this? > > JimG, can you please comment on the MachO

> There's still a problem for Darwin, or any other platform that use > subsections-via-symbols type layout tricks, though. There's no assembler- > time way to know how far apart the atoms in the section will be at > runtime, as the linker can, and will, move things around. Hmm, yes that does sound quite tricky. How do we currently deal with that for other pc-relative loads.

On Nov 1, 2013, at 12:15 PM, David Peixotto <dpeixott at codeaurora.org> wrote: >>>>> I was thinking that without the .ltorg directive the constant pool >>>>> would go at the end of the section. >>>>> >>>> So where does the assembler place the constant pool(s) if that >>>> directive isn't present? I was under the

On Thu, Oct 21, 2010 at 7:50 AM, Rafael Espíndola <rafael.espindola at gmail.com> wrote: >> Hmm, I wish we had this discussion way earlier.. >> >> How would I emit things in different subsections? I can do a high >> level switch to .ARM.attributes, and if I were emitting one blob from >> begin to end, using the higher level interface would be preferable,

> >>> I was thinking that without the .ltorg directive the constant pool > >>> would go at the end of the section. > >>> > >> So where does the assembler place the constant pool(s) if that > >> directive isn't present? I was under the impression it was always > required. > > > > From my understanding it is not required. I see

> > Hi Jim, > > > > Thanks for the review. It seems like you were looking at an old patch. > > I've attached the latest patches to this email (and a squashed version > > of all three for easy reading). I believe many of your concerns were > > addressed. See below for a detailed response. > > > Ack! Sorry about that. That would certainly explain some

Hi, I'm trying to implement a 10-bit relocation that does not start at the beginning of a byte-boundary and I'm not entirely sure I understand the use by some targets of MCFixup.Offset and MCFixupKindInfo.TargetOffset. LLVM's documentation states that: MCFixup.Offset -"/// The byte index of start of the relocation inside the encoded instruction."