similar to: [LLVMdev] Summary of TableNextGen BOF

On Tue, Dec 10, 2013 at 6:38 AM, Mihail Popa <mihail.popa at gmail.com> wrote: > Hello everyone. > > I apologise for the sizeable delay in sending this. > > The BoF was attended by quite a lot of people and there was general > agreement that tablegen needs improvement in some shape of form. However > there are many divergent ideas as to how to go about this improvement.

Hi, I'm not sure how to handle some of the trickier instruction encodings in MIPS64r6. My problem is that some instructions determine the operation based on the relationship between two fields. For example, 'beqc $rs, $rt, offset' (branch if equal, no delay slot) and bovc (branch if addition would overflow, no delay slot) share the same major opcode and field layout. When the register

Hi. Please see attached for review two patches related to ARM TrustZone. The first patch (LLVM-705.trustzone.patch) declares a new subtarget feature for TrustZone and adds it as requirement for the Secure Monitor Call instruction. The second patch (LLVM-706.trustzone_cortex.patch) applies the newly created feature to the relevant processors. Regards, Mihai Popa -- IMPORTANT NOTICE: The contents

HI group. I was wondering why the "trap" instruction is implemented in the ARM backend as an undefined opcode. For ARM mode, it uses 0xe7ffdefe, for Thumb 0xdefe. Why not use the BKT #imm instruction? Does anybody remember the reason behind this? Thanks, Mihai -------------- next part -------------- An HTML attachment was scrubbed... URL:

Can you elaborate on the fix you are thinking of? I'm not sure what you're thinking should change. On Tue, Nov 19, 2019 at 3:51 PM Quentin Colombet <qcolombet at apple.com> wrote: > It sounds to me that we should fix SDISel to accept both physical and > virtual definitions on variadic instructions. Though I wouldn’t bother > adding the support for implicit virtual

I agree, but I have no experience with LLVM doc. The job is very simple: add link at page https://github.com/draperlaboratory/fracture/wiki/How-TableGen%27s-DAGISel-Backend-Works into doc page http://llvm.org/docs/TableGen/BackEnds.html But how I can do it? On Tue, Jun 3, 2014 at 4:41 PM, Renato Golin <renato.golin at linaro.org> wrote: > Hi Daniil, > > Those look great! I think

Hi all, At the EuroLLVM BoF people asked where the design discussions around GlobalISel take place. Naturally, a lot of them take place at Apple, since they have the highest density of co-located GlobalISel devs, but we also have some in Phab. For those of you that are interested, please have a look at the following topics - discussions are progressing rather slowly and we definitely

Hi again, On 1 April 2017 at 15:09, Diana Picus <diana.picus at linaro.org> wrote: > If people feel it would be useful, we could also try to send a > weekly-ish email listing the pending reviews and any points that need > coordination. We're open to any suggestions on how we can communicate > better. Nobody said anything about this, but with people coming back from spring

I have pushed almost all the changes for the mips16 port and it passes about 90% of the single source tests from test-suite. It is still an experimental port but I am working hard to finish up the last details as soon as possible. Some things that are incomplete: 1) It is using soft float at this time. I did not like the gcc mips16 floating point design and will do something much better for

Hello. Sometimes the constraints imposed on an instruction's encoding are too complex to be described in tablegen alone. In such cases a custom decoder method is implemented. This makes sense when the decoding itself is very complex, but it is wasteful to do it only when checking additional constraints. This is because: 1. a custom decoder method has to decode operands, set opcodes, etc. -

> For those doing new ports, you might be interested to study how I did the td > files for mips16. There is still some cleanup I will do but essentially I > have cleanly layered the abstraction into four layers: > 1) machine formats > 2) assembly syntax > 3) instructions (none with patterns) > 4) patterns. Maybe you could write a bit more in-depth about this?

I note that there was a talk recently at EuroLLVM SPIR-V and LLVM about and so I want to get this message out soon so as to avoid duplicated effort. I have an up to date backend for SPIR-V on an up to date fork (~2-3 weeks behind) of LLVM, transplanted and “modernised” from Khronos’ SPIRV-LLVM that I plan on integrating into LLVM trunk. While it is usable in it’s current form there are several

When I registered for dev conference, there was a field asking what I was particularly interested in learning. I didn't fill it out then , but it occurs to me now that I'd really enjoy a tutorial on how to develop a new back end. I spent some time recently reviewing existing material (documentation and code) and not making a lot of progress. Indeed, under some time pressure, I'm

Hi Mihail, > static DecodeStatus CheckNEONConstraint(const MCInst &Inst, unsigned Insn) [...] > ConstraintCheckMethod = "CheckNEONConstraint" In general I like the idea of an instruction-validation method. I think it could also potentially solve the SoftFail/UNPREDICTABLE issues that are looming (and partially resolved for decoding at present). However, I think that to cope

> On Nov 29, 2018, at 01:57, Nicolai Hähnle <nhaehnle at gmail.com> wrote: > > Hi Daniel, > > > On 27.11.18 18:59, Daniel Sanders wrote: >> I've more or less finished updating the examples to the DAG style we were talking about. Hopefully I haven't forgotten anything, there was a lot to keep track of :-). Overall, I think there's a couple places where

Hello, I have a data.frame > names(popA) [1] "Year" "Series" "Age" "WM" "WF" "HM" "HF" "BM" [9] "BF" "IM" "IF" "AM" "AF" "Yr" how do i loop over a subset of variables in this frame to create a vector of

The saga continues. I've been tracking the interface changes and merging them with the refactoring work I'm doing. I got as far as building stage3 of llvm-gcc but the object files from stage2 and stage3 differ: warning: ./cc1-checksum.o differs warning: ./cc1plus-checksum.o differs (Are the above two ok?) The list below is clearly bad. I think it's every object file in the

Hello, We have published two papers which build upon the LLVM Compiler Infrastructure. Would it be possible to include them in the LLVM related publications at http://llvm.org/pubs/ ? I attach below the bibliographic references: "CERE: LLVM Based Codelet Extractor and REplayer for Piecewise Benchmarking and Optimization" P. de Oliveira Castro, C. Akel, E. Petit, M. Popov, and W.

Hello, I would like to submit two papers that use LLVM to the Related Publications section. Both papers focus on code isolation applied to perform piecewise compiler optimizations. The code isolation process is performed by CERE, an open source tool based on LLVM. The second paper is an extended version of the first one. 1) Piecewise Holistic Autotuning of Compiler and Runtime Parameters

Folks, OLS is fast approaching. There is a session on virtualization at the Kernel Summit, with Keir and Zach invited, which will probably last an hour(?). There is also a Xen BoF currently scheduled (Thursday, 7/20, 7:00PM) which will cover Xen specific issues. And there are approximately 3 or 4 paper presentations on related subjects. None of the above are going to allow for adequate time to