similar to: [LLVMdev] [Target] Custom Lowering expansion of 32-bit ISD::SHL, ISD::SHR without barrel shifter

I forgot to mention that I used EXTRACT_ELEMENT in my backend to get the high and low parts of an SDValue. On 10 Nov 2013, at 17:50, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation

I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation on the 2 8-bit subregs of that 16-bit register. That means the only practical solution for 32-bit shifts is to lower to a libcall but my situation for 16-bit shifts sounds similar to yours for 32-bit shifts. I

Hi Steve, Thanks for confirming that EXTRACT_ELEMENT is something I can use. I had seen it in the generated DAGs but was unsure whether I was "allowed" to use it, if that's the right word. I checked up on it more and indeed the mainstream targets like ARM use that node type in custom lowering code, so that should solve that. Perhaps in the future I might submit a patch for

Thanks for the suggestion, Duncan. I recently figured out that it had to do with how I was removing the pseudo instruction in my overridden expandPostRAPseudo() implementation. // member function's signature bool TheInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator p_mi) // works bb.erase(p_mi); // produces the assertion / memory leak. p_mi->removeFromParent(); I should have

removeFromParent just unlinks it from the basic block and returns the removed instruction. It does not delete it. On Sun, Jan 20, 2013 at 9:54 PM, David Waggoner <mathonnapkins at gmail.com>wrote: > > Thanks for the suggestion, Duncan. > > I recently figured out that it had to do with how I was removing the > pseudo instruction in my overridden expandPostRAPseudo()

LLVM appears to support Library functions for ISD::SRA ,ISD::SHL, and ISD::SRL, as they are properly defined in RuntimeLibCalls.def. The library functions defined in RuntimeLibCalls.def (among others) are these: HANDLE_LIBCALL(SRA_I16, "__ashrhi3") HANDLE_LIBCALL(SRA_I32, "__ashrsi3") HANDLE_LIBCALL(SRA_I64, "__ashrdi3") However, setting

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Hello, I've made some fair progress on a target for 6502 family CPUs recently, but I've run into an error I'm not sure how to address. I've ruminated over it for about a week now, trying various things and not having any success. It seems to scale with the number of routines in my .ll file, which I am trying to run through llc. I get the following stack dump from an assertion:

I am new to Rails and Ruby, and to OO languages, and seem to be making a very silly mistake somewhere here. Can anybody help? I am trying to write an application which involves ''exercises'', each of which consists of several ''templates''. This is based on MySQL tables with these names. I have models and controllers, built with the Rails Scaffold, for both

Hi, I was looking around the LLVM instruction set and I failed to find ROL and ROR instructions. Is there any plans on adding these instructions to LLVM? The reason that I am asking is for cryptographical algorithms which are becoming ever more important rotation is a major operation. Thus including such instruction could reduce 3 instructions {shl, shr, or} into {rol | ror} which could gain

Hi David, > Previously, I had been testing with only one routine per test .ll file, but I > thought I'd reached a point where I could test multiple operations at once and > understand the output. The odd part about this is that the likelihood of seeing > the above assertion scales with the number of functions in the .ll file. If I > have one or two functions, I never see it.

Hi Eli, Thanks for pointing to the CTLZ_ZERO_UNDEF “LibCall” implementation. I have not it in the version that I am currently using, so it’s nice to know that it’s implemented now. Incidentally, the CTLZ… implementation is IDENTICAL to what I am proposing for the Shifts. This is not just adding support for “out-of-tree-targets”, but giving consistency to the fact that we have perfectly defined

On Feb 3, 2009, at 2:35 PMPST, Mike Stump wrote: > On Feb 3, 2009, at 2:28 PM, Kasra wrote: >> I was looking around the LLVM instruction set and I failed to find >> ROL and ROR instructions. Is there any plans on adding these >> instructions to LLVM? > > Not sure what you mean: He's referring to the LLVM IR, I think, and it's true that doesn't have

--- On Tue, 2/3/09, Bill Wendling <isanbard at gmail.com> wrote: > From: Bill Wendling <isanbard at gmail.com> > Subject: Re: [LLVMdev] rol/ror llvm instruction set > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Cc: kasra_n500 at yahoo.com > Date: Tuesday, February 3, 2009, 2:52 PM > On Tue, Feb 3, 2009 at 2:45 PM, Dale Johannesen

On Tue, Feb 3, 2009 at 2:45 PM, Dale Johannesen <dalej at apple.com> wrote: > > On Feb 3, 2009, at 2:35 PMPST, Mike Stump wrote: > >> On Feb 3, 2009, at 2:28 PM, Kasra wrote: >>> I was looking around the LLVM instruction set and I failed to find >>> ROL and ROR instructions. Is there any plans on adding these >>> instructions to LLVM? >>

Hi all. Unfortunately, the existing quota-fs does not know how to get GROUP quota with NFS storage. But there is a tool for Linux quota-tools (http://slackware.rol.ru/slackware/slackware-12.2/source/a/quota/). This patch is made on the basis quota-tools. The patch was successful alpha testing. Suggestions and comments are welcome. -------------- next part -------------- An embedded and

The company I work for uses quiet some ARM processors and I am trying to convince them to let me spend some company time building an llvm back end :-) I have read the documentation and taken a look on the X86 back end. It looks quiet simple to get a very minimal back end working. I am considering for a first version: 1) only support the 32 bits ABI 2) Ignore the shifter (i.e use only 8 bits

On Feb 3, 2009, at 2:28 PM, Kasra wrote: > I was looking around the LLVM instruction set and I failed to find > ROL and ROR instructions. Is there any plans on adding these > instructions to LLVM? Not sure what you mean: $ cat t.c unsigned int rol(unsigned int i) { return i << 1 | i >> 31; } mrs $ clang -S t.c -O2 mrs $ cat t.s .text .align 4,0x90 .globl _rol

On Feb 3, 2009, at 3:54 PM, Kasra wrote: > I guess the backends could know about the instructions. But I am not > convinced why it is beneficial not to have ROR and ROL instructions > within llvm. > How would it be beneficial to have them, if we already generate them at the target level properly? Adding instructions "just because" doesn't seem wise. -Owen

Hola, gracias por la respuesta. Yo también puedo descargar el fichero pero no lo carga de forma correcta: > drive_download(" https://drive.google.com/file/d/1iN7rT-W8WoXsdBpKzxcatFx7nGPWNkuz/view?usp=sharing ", + overwrite = TRUE, verbose = TRUE) File downloaded: * restaurant.RData Saved locally as: * restaurant.RData > restaurant <-