similar to: [LLVMdev] Emitting x86 Multi-Byte NOP in MachineFunctionPass

Hi llvm-dev (cc google-xray), As a follow-up to the first XRay RFC [0] introducing the technology, I've been able to recently implement a functional prototype of the major parts of the XRay functionality [1]. This RFC is limited to exploring potential alternatives to the current LLVM-side changes, with the interest of getting clear guidance for landing the changes first in LLVM. Background /

Hi. I need to write a function pass that insert nop instruction in function. Examples of these instructions are: %nop = add i1 0, 0 or %nop = alloca i1, i1 0. This link couldn't help me: http://llvm.org/docs/ProgrammersManual.html#creating-and-inserting-new-instructions I need a clear example about inserting new instruction. Anyone can help me? Thanks. -------------- next part --------------

My pass runs after optimization passes. On Thu, Jul 9, 2015 at 1:11 PM, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote: > Hi, > > What are you trying to achieve? Inserting NOPs into LLVM IR is likely to > be pointless, as optimisations (in the IR or SelectionDAG) will remove them > before machine code generation. If you want to insert NOPs into the > generated

Dear All, I'm enhancing a MachineFunctionPass that enforces control-flow integrity. One of the things I want to do is to set the alignment of an instruction (by adding NOPs before it in the MachineBasicBlock or by emitting an alignment directive to the assembler) if it causes a specific sequence of bytes to be generated at a specific alignment. The goal is to ensure that sequences of

Dear All, To add to this, you can find examples of inserting NOPs for X86 in the CFI pass originally written at Lehigh University that we ported to 64-bit X86 for SVA: https://github.com/jtcriswell/SVA/blob/master/llvm/lib/Target/X86/X86CFIOptPass.cpp Alternatively, you could use an InlineAsm call at the LLVM IR level (which I think would be easier to implement). Regards, John Criswell On

I would like to convert a C file that uses OpenMP library to X86 code with a condition: I want to insert a NOP before each instruction that does a private memory access.I have written an optimization pass that inserts an inline assembly call (NOP) but it is applied at IR level, and I cannot determine where to insert it. How can I use LLVM to add NOPs accordingly? Thanks. --------------

This seems to be what I am looking for. That was very helpful. Thank you. Erdem From: vlknkls at gmail.com Date: Wed, 16 Sep 2015 16:25:29 +0000 Subject: Re: [llvm-dev] How to add NOP? To: erdemderebasoglu at hotmail.com; llvm-dev at lists.llvm.org Use MachineInstr::memoperands() function to get memory operands then you can get the address space by using MachineMemOperand::getAddrSpace(). Volkan

> On Nov 21, 2019, at 14:23, Robinson, Paul via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Some years ago there was a random-nop-insertion pass (for ROP gadget removal) proposed, which didn't stick; we recently had a summer intern work on it but did not get to proper quality; I'd like to revive that. Hi Paul, I'm curious about what the use case for this was. In

Hi Erdem, Since it is a target specific pass, you should put your pass inside the target's folder (e.g. lib/Target/X86/) and declare your pass in Target.h. Then you need to modify the target's TargetPassConfig ( http://llvm.org/docs/doxygen/html/classllvm_1_1TargetPassConfig.html) to enable your pass. You can check out the existing MachineFunction passes (e.g. X86ExpandPseudo.cpp) to get

On 10/23/2012 1:58 PM, John Criswell wrote: > Dear All, > > I'm enhancing a MachineFunctionPass that enforces control-flow > integrity. One of the things I want to do is to set the alignment of > an instruction (by adding NOPs before it in the MachineBasicBlock or > by emitting an alignment directive to the assembler) if it causes a > specific sequence of bytes to be

Hi, in section B.29. (Write State Register Instructions) of 'The SPARC Architecture Manual Version 8' it is said that the "The write state register instructions are delayed-write instructions." The Y-register is a state-register. Furthermore in the B.29-secion there is a programming note saying: MULScc, RDY, SDIV, SDIVcc, UDIV, and UDIVcc implicitly read the Y register.

Hi, I'm trying to follow the instructions on how to add a new bitcode instruction: http://llvm.org/docs/ExtendingLLVM.html This is my first foray into the guts of LLVM and I'm not sure I'm doing things the right way. I came up with a patch that adds a NOP (no operation) that will work with llvm-as, llvm-dis, and lli. It would be nice if one of the experts could take a look and give

What function provides the encoding length? X86 in particular is so difficult to encode that only the old style JIT and the MC Code Emitter could possibly know how many bytes something takes. On Tue, Oct 23, 2012 at 11:58 AM, John Criswell <criswell at illinois.edu>wrote: > Dear All, > > I'm enhancing a MachineFunctionPass that enforces control-flow integrity. > One of the

On 10/23/12 7:19 PM, Craig Topper wrote: > What function provides the encoding length? X86 in particular is so > difficult to encode that only the old style JIT and the MC Code > Emitter could possibly know how many bytes something takes. The getSize() method of MCInstrDesc which can be fetched from a MachineInstr using the getDesc() method:

Ok I see. Of course, at runtime, it's enough for dynamic linking or for deoptimization. However, wmkit acts both as a jit and as an aot. For the aot, it means that I can not use patchpoint and that I should have two different compilation strategy. It's not so difficult, but in this case, I can not use patchpoints to generate gc's stackmap for the aot (basically, I think that I could

I found that : "Code generator passes are registered and initialized specially by TargetMachine::addPassesToEmitFile and similar routines, so they cannot generally be run from the *opt* or *bugpoint* commands."...So how I can run a MachineFunctionPass? In the end, I just want to apply a DFS on a CFG of a function. And I need oriented edges and wanted to use

I am seeing a problem with the way nops are emitted in the integrated assembler for ARM. When switching from arm to thumb mode in an assembly file we still emit the arm nop opcode. Look at this small example: $ cat align.s .syntax unified .code 16 foo: add r0, r0 .align 3 add r0, r0 $ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o && llvm-objdump -triple thumbv7 -d

Hello everyone, I have written several complex passes till now, but I cannot write a MachineFunctionPass pass. It just gives me segfault. Hence I reduced the pass to the following form : using namespace llvm; namespace { class CFGexplorator : public MachineFunctionPass { public: static char ID; // Pass identification, replacement for typeid CFGexplorator() : MachineFunctionPass(ID)

Deer All, I wanted to write MachineFunctionPass which needs to be run after global register allocation pass. I have read LLVM documentation and blogs and able to write simple pass which will is invoked through opt command line. However, I could able to find any blogs or document to explains clear steps for writing MachineFunctionPass. Please suggest some documents or blogs which will help me

Yes, global variables are the only way to access shared memory. I'm just trying to get an idea of what you're aiming to accomplish to see if we can improve on the interface here. A MachineFunctionPass runs after instruction selection and relying on doInitialization to run before instruction selection is an implementation detail that I do not believe is guaranteed anywhere (I could be