similar to: [LLVMdev] [OT] ARMv8 (AArch64) server

Hi all I think the ARMv8 isa is awesome, but just wondering if anyone is doing the work around llvm (besides Apple). I've heard rumors, but not sure how far along any of those projects are. Anyone who needs a Fortran compiler for it or is interested to work together ping me off list please. Thanks Christopher

Hello. I would like to build some examples for ARM SVE. I see the support for SVE is available in the AArch64 back end of the latest LLVM. So I thought of using the latest LLVM distribution (revision 352287 from Jan 2019) and not rely on the ARM HPC compiler from https://developer.arm.com/products/software-development-tools/hpc/arm-cpp-compiler. Following

CALL FOR PAPERS ================================================================= LLVM-HPC: The LLVM Compiler Infrastructure in HPC http://llvm-hpc-workshop.github.io/ November 17th, 2014, New Orleans In conjunction with the 2014 ACM/IEEE Supercomputing Conference (SC'14)

Thanks Peter and Tim. Being that said, can I be sure that for 64 bit arm architectures (e.g. arm cortex A57) the neon feature and auto-vectorization is supported as default by clang 5.0? Because for us these two features are deal breaking for compiler evaluation. Mit freundlichen Grüßen / Best regards Zeeshan Haider Chassis Systems Control, Engineering Software Coordination, Software

Hi all, Our asterisk PBX, randomly restarts all the channels of the E1 connection. It sends this message "There is no D-Channel, using channel 16 anyway".Then the asteisk recive (or it thinks it recives) yellow alarms at all the B-channels, after that it restart all the channels. When restarting the B-channels it cut all the conversations that is handling at that moment. Does anyone

Hello Thomas, I use the following configure command to link against Ne10 Eg: configure --host=arm-linux-gnueabihf --enable-intrinsics --with-NE10-libraries=${BUILD_NE10_LIB} --with-NE10-includes=${BUILD_NE10_INC}" So, in my normal testing, I explicitly specify where the NE10 header files are installed and where the NE10 libraries are installed. Looking back at configure.ac

Hello Timothy, Great to hear from you! Fired up my hardware today and this issue looks like a regression in Ne10 library. The commit in Ne10 [1] that I tested to be working successfully back in May 5b63074db45000f9688460990ee3f5e147d93782 which is the Patch Phil at ARM added to fix the overflow issue in nfft=60 case. After git-bisect, looks like the culprit patch in Ne10 [1] is

Hi there, I am Software product developer at Robert Bosch, Germany. We are using armv8 64bit targets for our development. We have the need to do the cross compiling for our target on windows. I have compiled clang 5.0 from the vcs git. I have tried compiling the code with following options set: clang.exe -target armv8 -fslp-vectorize-aggressive -mfpu=neon -mfloat-abi=hard -c test.cpp As you

I'm trying to get these cleaned up and landed, but I'm running into some trouble with this patch. Using commit a08b29d88e3c (July 21) of Ne10, I'm seeing test failures for 60-point FFTs: nfft=60 inverse=0,snr = -3.312408 ** poor snr: -3.312408 ** nfft=60 inverse=1,snr = -16.079597 ** poor snr: -16.079597 ** All other sizes tested appear to work fine (84 to 140 dB of SNR). This

Hi Timothy, Sorry for late reply. I have upstreamed the patch to fix the regression here: https://github.com/projectNe10/Ne10/commit/ee5d856cd9cb8c4a15ace567df4239f4e788d043 I have tested it with Vish's branch: http://git.linaro.org/people/viswanath.puttagunta/opus.git/shortlog/refs/heads/rfcv3_fft_fixed) Both unit test dft and unit test mdct passed on ARM v7/v8, floating point/fixed

One more thing, setting up clang 5,0 on windows, I have issues compiling libcxx project. Is it supported to be built with Visual studio or MinGW make files? Mit freundlichen Grüßen / Best regards Zeeshan Haider CC/ESM1 Tel. +49(711)811-47379 -----Original Message----- From: Tim Northover [mailto:t.p.northover at gmail.com] Sent: Freitag, 3. Februar 2017 18:05 To: Haider Zeeshan

On Fri, Feb 3, 2017 at 12:03 PM, Renato Golin <renato.golin at linaro.org> wrote: > Adding some people that know about libcxx and/or windows on arm. > Note that if you are trying to use Windows on ARM port, I've not tested C++ support with MS ABI, onlly the itanium ABI has been tested (there are known limitations for the C++ MS ABI on Windows ARM). Furthermore, we do not

Using GCC 4.9.2, decoding the opus test vector set 10 times. All tests pass. I will do longer tests later with a larger test set, but it looks good so far. I am having a lot of trouble with the Ne10 detection. Using the precompiled Ne10 binaries at http://people.linaro.org/~viswanath.puttagunta/opus/NE10_root/ Both NE10 and Ne10 capitalizations seem to be in use. Also, where should the NE10

I am trying to use t.test on the following data: date type INTERVAL nCASES MTF SDF MTO SDO nFST MF nOBS MO MB BIASCV BIASEV ME MAE RMSE CRCF 2001-06-15 avn GE1.00 4385 0.246 0.300 1.502 0.556 1367 1.373 4385 1.502 1.471 0.285 0.164 -1.256 1.266 1.399 0.056 2001-06-15 avn

Hi everyone, Colleagues of mine at Lawrence Livermore National Laboratory (LLNL), having seen the advantages of working closely with LLVM, have decided to toss their hat into the ring and would like to hire an LLVM-focused compiler engineer. I collaborate with LLNL regularly, and I'm excited that they're taking this step. I expect that a qualified applicant will find this position both

JinGu: I’m not Graham, but you might find the following link a good starting point. https://community.arm.com/developer/tools-software/hpc/b/hpc-blog/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture The question you ask doesn’t have a short answer. The compiler and the instruction set design work together to allow programs to be compiled without knowing

Dear everyone, Your code is slow and you are interested in performance optimization for scientific software? Figuring out where’s the bottlenecks guided by performance evaluation tools. If you are interested in porting your code to a HPC hardware platform and architecture, than OpenACC as a user-driven directive-based performance-portable parallel programming model might be a solution. What are

This idea is intruiging... Suppose one has a set of file servers called A, B, C, D, and so forth, all running CentOS 6.5 64-bit, all being interconnected with 10GbE. These file servers can be divided into identical pairs, so A is the same configuration (diks, processors, etc) as B, C the same as D, and so forth (because this is what I have; there are ten servers in all). Each file server has

On Sun, Jul 16, 2017 at 06:02:15PM +0100, Pete Biggs wrote: > > > > The physicists and mathematicians who count there need high durations. > > Yes. I too run HPC clusters and I have had uptimes of over 1000 days - > clusters that are turned on when they are delivered and turned off when > they are obsolete. It is crucial for long running calculations that you > have a

Dear Prof.Vikram. Really appreciate the hard work and determination in bringing LLVM concept. I had been a GCC contributor for almost 3-4 years, specially in backend with Renesas(SH) targets. Gone through http://llvm.org and found very challenging, seems to be better in many areas w.r.t GCC. Seeing the work of LLVM, am motivated to contribute to LLVM with reference to HPC needs. I maybe slow to