similar to: [LLVMdev] Inserting a synchronisation before volatile and atomic loads

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Inserting a synchronisation before volatile and atomic loads"

2015 Feb 26
0
virtio balloon: do not call blocking ops when !TASK_RUNNING
Thomas Huth <thuth at linux.vnet.ibm.com> writes: > Hi all, > > with the recent kernel 3.19, I get a kernel warning when I start my > KVM guest on s390 with virtio balloon enabled: The deeper problem is that virtio_ccw_get_config just silently fails on OOM. Neither get_config nor set_config are expected to fail. Cornelia, I think ccw and config_area should be allocated inside
2015 Feb 26
0
virtio balloon: do not call blocking ops when !TASK_RUNNING
Thomas Huth <thuth at linux.vnet.ibm.com> writes: > Hi all, > > with the recent kernel 3.19, I get a kernel warning when I start my > KVM guest on s390 with virtio balloon enabled: The deeper problem is that virtio_ccw_get_config just silently fails on OOM. Neither get_config nor set_config are expected to fail. Cornelia, I think ccw and config_area should be allocated inside
2015 Feb 25
7
virtio balloon: do not call blocking ops when !TASK_RUNNING
Hi all, with the recent kernel 3.19, I get a kernel warning when I start my KVM guest on s390 with virtio balloon enabled: [ 0.839687] do not call blocking ops when !TASK_RUNNING; state=1 set at [<0000000000174a1e>] prepare_to_wait_event+0x7e/0x108 [ 0.839694] ------------[ cut here ]------------ [ 0.839697] WARNING: at kernel/sched/core.c:7326 [ 0.839698]
2015 Feb 25
7
virtio balloon: do not call blocking ops when !TASK_RUNNING
Hi all, with the recent kernel 3.19, I get a kernel warning when I start my KVM guest on s390 with virtio balloon enabled: [ 0.839687] do not call blocking ops when !TASK_RUNNING; state=1 set at [<0000000000174a1e>] prepare_to_wait_event+0x7e/0x108 [ 0.839694] ------------[ cut here ]------------ [ 0.839697] WARNING: at kernel/sched/core.c:7326 [ 0.839698]
2012 Aug 14
0
[LLVMdev] Load serialisation during selection DAG building
Further to my earlier question, I'm perhaps a bit confused about memory serialisation. The following example, compiled using clang for the MSP430: target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16" target triple = "msp430-??-??" @y = common global i16 0, align 2 @x = common global i16 0, align 2 define void @f() nounwind { entry: %0 = load i16* @y,
2013 Oct 08
1
[LLVMdev] Post Increment Indirect Move Instructions
Hi Hal, On Tuesday 01 October 2013 06:22 PM, Hal Finkel wrote: > ----- Original Message ----- >> Hi Hal, >> >> >> Our Architecture has indirect move instruction which increments >> the >> pointer implicitly and the target only has i8 type values. So the >> load >> of i16 will be converted to two i8 target loads wherein after the
2012 Aug 13
0
[LLVMdev] Load serialisation during selection DAG building
Steve, I had created a patch last year that does something similar to what you describe for regular loads and stores using aliasing information. I think that the last message in the thread was: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120402/140299.html This approach has worked for me, but it is not the preferred solution going forward. The preferred solution is to keep the
2012 Aug 13
3
[LLVMdev] Load serialisation during selection DAG building
I've got a question about how SelectionDAGBuilder treats loads. The LLVM Language Reference Manual explicitly states that the order of volatile operations may be changed relative to non-volatile operations. However, when the SelectionDAGBuilder in LLVM 3.1 encounters a volatile load, it flushes all pending loads and then chains the volatile load onto them meaning that the volatile load must
2012 Aug 14
2
[LLVMdev] Load serialisation during selection DAG building
I looked into those patches but I don't think they will help in my situation because my problems occur during instruction selection rather than scheduling. A simple and concrete example is a pattern like: [(set GR:$dst (add GR:$src (nvload addr:$mem)))] where nvload matches a load provided that isVolatile() is false. If the selection DAG looks like: | | LD1 LD2 ^
2012 Nov 26
1
A problem subsetting a data frame
Hi all, I have this microarray large microarray data set (ALL) from which I would like to subset or extract a set of data based on a factor ($mol.biol). I looked up some example of subsetting in, picked up two commands and tried both but I got error messages as follows > testset <- subset(ALL, ALL$mol.biol %in% c("BCR/ABL","ALL1/AF4")) >> Error in
2008 Aug 16
1
Bionic Commando: Rearmed fails on startup
System Specs wine version: 1.1.0 OS: Gentoo with Linux 2.6.24 Nvidia Drivers: 169.12 wine configs * tried with virtual desktop * tried with WinXP and Vista I was able to install Bionic Commando: Rearmed. However, wine fails when I attempt to start the game with the output shown below. Code: fixme:ntdll:NtQueryInformationProcess (0xffffffff,info_class=34,0x1c3a3b0,0x00000004,0x1c3a3ac)
2017 Nov 20
2
Meaning of loads/stores marked both atomic and volatile
Hi Tim, On 20 November 2017 at 16:41, Tim Northover <t.p.northover at gmail.com> wrote: > There are only a couple of valid uses for volatile these days Do you mean volatile used alone or also the combination 'atomic volatile'? It think that 'atomic volatile' is very useful. Consider following pseudo-code examples, where all loads and stores are atomic (with some memory
2017 Nov 20
4
Meaning of loads/stores marked both atomic and volatile
Hi llvm-dev, I read about volatile and atomic modifiers in the docs[1], and I feel they make sense to me individually. However, I noticed that store[2] and load[3] instructions can be marked as both volatile and atomic. What's the use case for using both volatile and atomic on an instruction? Isn't it the case that atomic implies volatile? I guess it isn't, but I don't understand
2010 Nov 03
0
[LLVMdev] Fw: Forcing the Interpreter segfaults
Hi Salomon, please don't forget to reply to the list too (I've CC'd the list). > I don't think my code is doing anything worng... No, it looks fine to me, and the interpreter certainly supports this. That suggests that the value of %str is not being transmitted to the function right. If it is getting the wrong pointer value, that would explain why it barfs. Ciao, Duncan.
2011 Aug 26
2
[LLVMdev] Dead node removal in DAGCombiner
Is this piece of code in DAGCombiner::visitLOAD removing a dead node? 06155 if (N->use_empty()) { 06156 removeFromWorkList(N); 06157 DAG.DeleteNode(N); 06158 } If it is, is there a reason it doesn't push its operands to the work list as done in line 974-975? 00970 // If N has no uses, it is dead. Make sure to revisit all N's operands once
2017 Aug 03
2
Dependence analysis - missing loop-carried dependencies?
Hi, I'm trying to do some (loop-carried) dependence analysis using LLVM, but I'm confused by the results I'm getting. For example, consider this simple C program: int main(){ for (int i = 0; i < 10; ++i) { } return 0; } I would expect that the loop comparison depends on the loop initialisation and the loop update, however I only see a dependence to the loop initialisation.
2011 Aug 26
0
[LLVMdev] Dead node removal in DAGCombiner
Hi Akira, > Is this piece of code in DAGCombiner::visitLOAD removing a dead node? > > 06155 if (N->use_empty()) { > 06156 removeFromWorkList(N); > 06157 DAG.DeleteNode(N); > 06158 } yes. > If it is, is there a reason it doesn't push its operands to the work > list as done in line 974-975? > > 00970 // If N has no uses,
2011 Jun 24
0
[LLVMdev] Infinite loop in llc on ARMv7 (LLVM HEAD from June 17)
On Fri, Jun 24, 2011 at 9:12 AM, Karel Gardas <karel.gardas at centrum.cz> wrote: > Hello, > > it looks like I do have infinite loop in llc on linux/armv7 platform > somewhere in llvm::SmallVectorImpl. Two backtraces obtained with 10 > seconds delay are: > > 0x0099be14 in llvm::SmallVectorTemplateCommon<llvm::SDNode*>::setEnd > (this=0x7ee90b38, P=0x5c06988)
2008 Oct 02
1
Bionic Commando Rearmed
I have made the daring (and possibly idiotic) decision to play BCR on my laptop instead of my desktop computer, as my desktop is single core and therefore runs the game rather sluggishly while my laptop is dual-core. The only problem with this is that my laptop runs Linux. Does anyone knwo what I might have to tweak in order to get it to run? Will I have to disable SecuROM?
2011 Jun 24
2
[LLVMdev] Infinite loop in llc on ARMv7 (LLVM HEAD from June 17)
Hello, it looks like I do have infinite loop in llc on linux/armv7 platform somewhere in llvm::SmallVectorImpl. Two backtraces obtained with 10 seconds delay are: 0x0099be14 in llvm::SmallVectorTemplateCommon<llvm::SDNode*>::setEnd (this=0x7ee90b38, P=0x5c06988) at /export/home/karel/vcs/llvm-head/include/llvm/ADT/SmallVector.h:103 103 void setEnd(T *P) { this->EndX = P; }