similar to: [LLVMdev] Out of tree targets: Possibly additional API to implement for out of tree targets using the IfConverter

On Apr 26, 2013, at 3:53 AM, Martin J. O'Riordan <Martin.ORiordan at movidius.com> wrote: > I am migrating the llvm/clang derived compiler for our processor from the > v3.1 to v3.2 codebase. This has mostly gone well except that instruction > latency scheduling is no longer happening. > > The people who implemented this previously sub-classed 'ScheduleDAGInstrs'

Hi everyone, The MachineLICM pass has a heuristic such that, even in low-register-pressure situations, it will refuse to hoist "cheap" instructions out of loops. By default, when an itinerary is available, this means that all of the defined operands are available in at most 1 cycle. ARM overrides this, and provides this more-customized definition: bool ARMBaseInstrInfo::

On Tue, Nov 17, 2015 at 11:15 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 11/17/2015 12:26 PM, Rail Shafigulin wrote: > >> >> I tried setting >> let mayLoad = 1 { >> class InstrLD .... { >> } >> } >> >> But that didn't seem to work. When I looked at the debug output the >> latency for the load

We'd like to be able to vary the latency of our load instructions based on what address space is being loaded from. I was thinking I could do this by overriding getOperandLatency in our target, but I'm wondering if the addrspace info is available when instructions are scheduled? For example, I have this in our llvm IR: %0 = load i32 addrspace(4)* @answer, align 4 store i32 %0, i32*

On Jun 8, 2012, at 12:52 PM, Marc J. Driftmeyer <mjd at reanimality.com> wrote: > I keep getting this error upon building: > >> Linking CXX executable ../../bin/opt >> ../../lib/libLLVMTarget.so: error: undefined reference to 'llvm::TargetInstrInfo::getNumMicroOps(llvm::InstrItineraryData const*, llvm::MachineInstr const*) const' >>

I keep getting this error upon building: > Linking CXX executable ../../bin/opt > ../../lib/libLLVMTarget.so: error: undefined reference to > 'llvm::TargetInstrInfo::getNumMicroOps(llvm::InstrItineraryData > const*, llvm::MachineInstr const*) const' > ../../lib/libLLVMTarget.so: error: undefined reference to >

Thank you, Mr. Criswell. It actually worked but now this tblgen cannot find 'TargetSchedule.td' which is in the folder where 'Target.td' is in, as follows: Included from ARM.td:18: Parsing ../Target.td:121: Could not find include file 'TargetSchedule.td'! The location of 'Intrinsics.td' is different from that of 'Target.td'. How can I deal with this in

Hi, I am trying to debug my backend, and observe very strange behavior with dbgs(): In the IfConverter, I have added two debugging lines that print floating-point numbers for the sake of demonstration that such printing works fine. bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, unsigned Cycle, unsigned Extra, const BranchProbability

Hello! The if-converter tries to match 'Simple' patterns looking like this: // Simple (split, no rejoin): // EBB // | \_ // | | // | TBB---> exit // | // FBB The IfConverter::ValidSimple method (lib/CodeGen/IfConversion.cpp:461) checks if TBB matches this pattern. It basically does this by simply checking if AnalyseBranch fails on

Hi, that solved my problem on trunk as well, thanks. Strange that you have to include this though. Bjorn On 27 Nov 2012, at 00:00, Daniel Prokesch <daniel.prokesch at gmail.com> wrote: > Hi, > > I accidentally stumbled upon your post. > I observed similar behaviour whenever I did not include > > #include "llvm/Support/Debug.h" > #include

Can you try making the constructor "explicit" for PrintReg in include/llvm/Target/TargetRegisterInfo.h. I think you were getting an implicit conversion there which should probably be fixed anyway. On Mon, Nov 26, 2012 at 11:47 PM, Bjorn De Sutter < bjorn.desutter at elis.ugent.be> wrote: > Hi, > > that solved my problem on trunk as well, thanks. Strange that you have to

On Tue, Jan 10, 2017 at 2:31 AM, Peter A Jonsson <pj at sics.se> wrote: > Hi Kyle, > > my apologies for mailing you directly but it seems new user creation is > disabled on the llvm bugzilla. > > We sometime lose edges during IfConversion of diamonds and it’s not > obvious how to reproduce on an upstream target. The documentation for > HasFallThrough says *may*

Dear all, I use the clang frontend to produce the control flow graph of a C program through this command: clang -Xclang -analyze -Xclang -analyzer-checker=debug.DumpCFG test.c The produced information contains all the basic blocks identified by labels, e.g. B1, B2, etc. along with their predecessors and successors. Is there a way to get the starting address of each of these basic block? I would

Dear Andrew and the Group, I’m trying come up with a SchedMachineModel for the AMD bulldozer http://en.wikipedia.org/wiki/Bulldozer_(microarchitecture). The model is not exist for the same .Please correct me if am i wrong here. I was going through your reference @ https://llvm.org/svn/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td . But I couldn’t model some of the

Hi Craig, I updated from the trunk some minutes ago, and thus got the "explicit". PrintReg constructor. When I do not include raw_ostream.h after including Debug.h in the backend cpp files, I now get compilation errors, not only when trying to print floats but also in other places. For example, for the code bool ADRESRegisterInfo::hasReservedCallFrame(const MachineFunction &MF)

Dear All, Attached files is related to the changes made to add the Schedmodel for a AMD bulldozer target, Please note that , the model is incomplete but has some of the valuables features implemented. Request to the group or someone from AMD for the comments on the implementation. Thanks ~umesh On Wed, Nov 13, 2013 at 8:14 PM, Umesh Kalappa <umesh.kalappa0 at gmail.com>wrote: >

I overrode getInstrLatency and did some printing to see what is available there. It looks like the registers are still virtual at that point when getInstrLatency is called - is that correct? (we needed to make some decisions based on actual registers that have been assigned since some registers are reserved as address space pointers and we could vary the latency based on which address space

Hi all, The goal of this RFC is to make information related to variant scheduling classes accessible at MC level. This would help tools like llvm-mca understand/resolve variant scheduling classes. To achieve this goal, I plan to introduce a new class of scheduling predicates named MCSchedPredicate. An MCSchedPredicate allows the definition of boolean expressions with a well-known semantic, that

On 09/25/2017 06:47 PM, David Keaton via llvm-dev wrote: > On 09/25/2017 06:19 PM, Matthias Braun wrote: >> >>> On Sep 25, 2017, at 6:03 PM, David Keaton via llvm-dev >>> <llvm-dev at lists.llvm.org> wrote: >>> >>> On 09/25/2017 02:53 PM, Matthias Braun via llvm-dev wrote: >> In the meantime `cmake

Dear all, Some benchmarking experimentation I`ve done recently -- all on AArch64 -- has shown that it might be beneficial for all AArch64 targets to have a positive LoopMicroOpBufferSize, whereas the default that applies to all ISAs seems to be zero. Although I`ve tried going as far down the rabbit hole as I can, I haven`t found a way to set DefaultLoopMicroOpBufferSize on a per-ISA basis or