similar to: [LLVMdev] Post Increment Indirect Move Instructions

Hi Hal, Our Architecture has indirect move instruction which increments the pointer implicitly and the target only has i8 type values. So the load of i16 will be converted to two i8 target loads wherein after the first load instruction, the pointer to the first i8 address will automatically increment to point to the next i8 value. So the post increment nature is in the Target. A normal

----- Original Message ----- > Hi, > > We have an architecture where the indirect move instruction > implicitly increments the pointer > value after the move. We have Instruction format and pattern for this > type of instructions. > > How to encode the information that the pointer is incremented? As you seem to be aware, LLVM has patterns specifically to match

----- Original Message ----- > Hi Hal, > > > Our Architecture has indirect move instruction which increments > the > pointer implicitly and the target only has i8 type values. So the > load > of i16 will be converted to two i8 target loads wherein after the > first > load instruction, the pointer to the first i8 address will > automatically >

Hi Hal, On Tuesday 01 October 2013 06:22 PM, Hal Finkel wrote: > ----- Original Message ----- >> Hi Hal, >> >> >> Our Architecture has indirect move instruction which increments >> the >> pointer implicitly and the target only has i8 type values. So the >> load >> of i16 will be converted to two i8 target loads wherein after the

Hi, I'm trying to enable the pre-decrementing and post-incrementing based addressing modes for my target. So far without any success :( I enabled these modes in my TargetLowering class using setIndexedLoadAction and setIndexedStoreAction calls. I also defined getPreIndexedAddressParts and getPostIndexedAddressParts. And I can see that DAGCombiner::CombineToPostIndexedLoadStore is invoked.

Hi Chris, --- Chris Lattner <sabre at nondot.org> wrote: > On Wed, 29 Nov 2006, Roman Levenstein wrote: > > Thanks, this is a good idea. > > > > But I cannot figure out how to make a machine function pass run > > _BEFORE_ the RA. I guess I'm missing something very obvious. > > In your target's TargetMachine::addInstSelector method, add it to the

----- Original Message ----- > From: "Bruce Hoult" <bruce at hoult.org> > To: "Johnny Val" <johnnydval at gmail.com> > Cc: "<llvmdev at cs.uiuc.edu>" <llvmdev at cs.uiuc.edu> > Sent: Thursday, October 23, 2014 8:31:35 AM > Subject: Re: [LLVMdev] Question regarding getElementPtr/Addressing modes in backend > > Many CPU

I have a rudimentary implementation for load and store instructions, where the memory address operand is automatically post-incremented when the load or store instruction is issued. However, this is currently coded using custom lowering, and explicit pattern matching in the 'ISelDAGtoDAG' implementation. But it seems to me that I ought to be able to achieve this exclusively using

Hi Steve, Thanks for the tip regarding MIOperandInfo, I didn't think of that part of the tablegen description. Sadly, I did actually mean: r1 = *(i0 += m0). So increment i0 by m0. Read memory the memory location "pointed" to by i0. Store in r1. Sadly I am not too familiar with compiler terminology, so I don't know if there is a proper term for such a load. On Thu, Oct 23,

I am trying to implement vector type load/store with post-increment for an out of tree backend. I see that that ARM NEON support such load/store so I am using ARM NEON as an example of what to do. The problem is I can't get any C or C++ code example to actually generate vector load/store with post increment. I am talking about something like this: vldr d16, [sp, #8] Does anybody

Hi, Is there a way to specify the Integer type to be of 2Byte for a Target? LLVM IR produces 4Bytes(i32) for Integer type. Clang can be tweaked to make the integer to be of 2Byte(i16), but is there a way to specify in the LLVM CodeGen? -- Thanks and Regards, Shashidhar

Hello. I fixed the bug reported in the previous post on this thread (<<llvm::MemSDNode::MemSDNode(unsigned int, unsigned int, const llvm::DebugLoc&, llvm::SDVTList, llvm::EVT, llvm::MachineMemOperand*): Assertion `memvt.getStoreSize() <= MMO->getSize() && "Size mismatch!"' failed.>>) The problem with this strange error reported comes from

Hello, I am Shashidhar SR Working for Siemens Communication Software in Bangalore, INDIA as a Configuration Manager for Clearcase. I need some help regarding the samba configuration at our site. First Let me Explain our Environment: - We are Using samba 2.2.8a on Solaris 9. - We are using samba as an interop from Solaris 9 box to winnt/w2k/win-xp clients. - On Solaris we have installed IBM

Hi Everyone, I am Shashidhar G, M.S. Research Scholar at Indian Institute of Technology Madras working in the area of Program Analysis and Compiling for Parallelization. I am interested in working with the LLVM community for GSOC 2016. I looked at the Open projects and i am interested to work in the area of Alias Analysis. I have implemented a simple version of Andersen's Analysis as LLVM

Shashidhar, Here's it for 32 and 64 bits. https://developer.apple.com/library/mac/#documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html#//apple_ref/doc/uid/TP40002492-SW4 https://developer.apple.com/library/mac/#documentation/DeveloperTools/Conceptual/LowLevelABI/140-x86-64_Function_Calling_Conventions/x86_64.html -Dmitry. On Tue, Feb 26,

Hi All, I am looking for a ABI Documentation of the X86 architecture to understand how LLVM converts its IR to X86 target instructions. Please guide me from where i can get the resources. Thanks, Shashidhar -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130226/05855007/attachment.html>

Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile -

Hi all, This is version three of the patches I previously posted here: v1: https://lore.kernel.org/lkml/20191108170120.22331-1-will at kernel.org/ v2: https://lore.kernel.org/r/20200630173734.14057-1-will at kernel.org Changes since v2 include: * Actually add the barrier in READ_ONCE() for Alpha! * Implement Alpha's smp_load_acquire() using __READ_ONCE(), rather than the other

Hi everyone, This is the long-awaited version two of the patches I previously posted in November last year: https://lore.kernel.org/lkml/20191108170120.22331-1-will at kernel.org/ I ended up parking the series while the READ_ONCE() implementation was being overhauled, but with that merged during the recent merge window and LTO patches being posted again [1], it was time for a refresh. The

Hi everyone, This is the long-awaited version two of the patches I previously posted in November last year: https://lore.kernel.org/lkml/20191108170120.22331-1-will at kernel.org/ I ended up parking the series while the READ_ONCE() implementation was being overhauled, but with that merged during the recent merge window and LTO patches being posted again [1], it was time for a refresh. The