Displaying 10 results from an estimated 10 matches similar to: "[LLVMdev] cannot build 3.3, problems with alternate architectures"
2013 Sep 25
1
[LLVMdev] arm64 / iOS support
Attached is a working patch set for llvm to be able to emit arm64
(currently as triple aarch64-apple-ios) mach-o object files, in case
someone is interested. I'm not sure if the llvm maintainers want the
patch given the previous message that there's going to be an official
patch set from apple to support this, but here is mine.
What works (tested on an iPhone 5S):
* objc strings,
2017 Oct 17
2
getCacheSize() / subtarget machine id
Hi,
while implementing SystemZTTI:getCacheSize(), it became clear that there
really isn't a simple way to just ask the Subtarget for the current
subtarget machine model. I was thinking like something of an enum that
would also reflect the subtarget series (and would allow >= and similar
operations).
I would like to ask what the ideas are on how this should be done best.
Some
2018 Nov 01
3
RFC: System (cache, etc.) model for LLVM
Am Do., 1. Nov. 2018 um 15:21 Uhr schrieb David Greene <dag at cray.com>>
> > thank you for sharing the system hierarchy model. IMHO it makes a lot
> > of sense, although I don't know which of today's passes would make use
> > of it. Here are my remarks.
>
> LoopDataPrefetch would use it via the existing TTI interfaces, but I
> think that's about it
2012 Nov 24
2
[LLVMdev] Fwd: Prevention register promotion at the isel codegen phase
Sorry, forgot to Reply-All.
Begin forwarded message:
> From: Steve Montgomery <stephen.montgomery3 at btinternet.com>
> Subject: Re: [LLVMdev] Prevention register promotion at the isel codegen phase
> Date: 24 November 2012 17:09:58 GMT
> To: Joseph Pusdesris <joe at pusdesris.com>
>
> I had a similar problem trying to implement reg-mem operations. The solution I
2012 Nov 24
0
[LLVMdev] Fwd: Prevention register promotion at the isel codegen phase
Yes, this is very helpful! Thank you!
How does this work when exiting a variable's liveness range? Will it
automatically know to free the stack slot for reuse?
-Joe
On Sat, Nov 24, 2012 at 12:23 PM, Steve Montgomery <
stephen.montgomery3 at btinternet.com> wrote:
> Sorry, forgot to Reply-All.
>
> Begin forwarded message:
>
> *From: *Steve Montgomery
2019 Apr 26
10
Automatically backing up and restoring x18 around function calls on AArch64?
Hi,
When using Wine to run Windows ARM64 executables on Linux, there's one
major ABI incompatibility between the two; Windows treats the x18
register as the reserved platform register, while it is free to be
clobbered anywhere in code on Linux.
The Wine code sets up this register before passing control over to the
Windows executable code, but whenever the Windows code calls a function
2017 May 01
4
Marking a register as reserved midway through register allocation
Hey all,
I'm attempting to rewrite something that the AVR backend used to support
(through an extremely dirty hack that was reverted before the upstreaming
of the target).
The removal of the hack can be seen on GitHub
https://github.com/avr-llvm/llvm/pull/226/files
On the AVR architecture, the stack pointer is not in a standard register,
but rather it is a special register which can only
2018 Nov 01
2
RFC: System (cache, etc.) model for LLVM
Hi,
thank you for sharing the system hierarchy model. IMHO it makes a lot
of sense, although I don't know which of today's passes would make use
of it. Here are my remarks.
I am wondering how one could model the following features using this
model, or whether they should be part of a performance model at all:
* ARM's big.LITTLE
* NUMA hierarchies (are the NUMA domains
2018 Jul 22
2
Finding scratch register after function call
>It should be possible to get llvm to produce very good code for the Z80...
Yes, I was thinking that too. These techniques didn't exist back then,
so I'm really looking forward to the point where the first regular C
sources can be compiled and see the magic happening in action live :)
------------------------------------------------------------------------
*From:* Bruce Hoult
2016 Aug 17
3
RFC: Disambiguate RegClass->getSize()
*** Problem
The documentation for function "getSize" in both MCRegisterClass and
TargetRegisterClass states:
/// getSize - Return the size of the register in bytes, which is also
the size
/// of a stack slot allocated to hold a spilled copy of this register.
The problem is that these two values are not always the same. For
example, Hexagon has predicate registers that are 8