similar to: [LLVMdev] TableGen and computed expressions

Martin hi. It seems like you have in fact understood the offered solution, and its disadvantages. The thing is, that as far as I understand Tblgen (and I think I do :-) ), The idea behind it is that records only have state (i.e., fields), and not a behavior (i.e., methods) - so dynamic evaluation can only be achieved by built-in functions. (e.g., !if(), !foreach() etc...). Maybe you can try

Martin hi. I encountered a similar problem, and made a solution for it. The solution is a tblgen enhancement, and enables tblgen code expressions to be dynamically evaluated. It works as follows: 1. Code expressions have 'special runtime evaluation' expression (very similar to strings in ruby), e.g.: code c = {[ My name is #{injected}. }. 2. I have added another command line switch for

Thanks again Elior, Yes, I tried using '!if', etc. but I just get type mismatches for the initializer (int) - probably something daft I'm doing :-( MartinO -----Original Message----- From: Malul, Elior [mailto:elior.malul at intel.com] Sent: 29 September 2013 09:19 To: Martin.ORiordan at movidius.com; llvmdev at cs.uiuc.edu Subject: RE: [LLVMdev] Tblgen and computed expressions

Thanks Elior, Sorry for the delay - emergencies never seem to go away in compiler development ;-) That sounds like an interesting approach, a kind-of pre-processor for TD files. But will this still not result in a constant, although externally provided, or have I misunderstood? What I would like to do is compute a different value depending on which '-target-cpu <cpu>' option was

Thanks for the quick answer Bruce. So far as I can tell (from a quick read), this is really for integrated assemblers/disassemblers - but we use an external assembler. When invoking clang we would provide ‘-mcpu=chip_v1’ or ‘-mcpu=chip_v2’, and the mnemonic ‘LD32’ is only valid when compiling for ‘chip_v1’, while ‘LD.32’ is only valid when compiling for ‘chip_v2’. But I will study the

----- Original Message ----- > From: "Elior Malul" <elior.malul at intel.com> > To: "Michael Gottesman" <mgottesman at apple.com>, "Hal Finkel" <hfinkel at anl.gov> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Thursday, February 14, 2013 8:33:42 AM > Subject: RE: [LLVMdev] SIMD

Hi LLVM Dev, I have an old problem that I've wanted to clean-up for some time. Our chip has gone through a number of iterations in the past few years, but with each revision there have been changes to some of the mnemonics for instructions. These are mostly very simple, for example we had a 32-bit load from memory instruction named 'LD32' in one version of the chip, but for a

First let me say that I really like the notion of being able to plug in .bc libraries into the compiler and I think that there are many potential uses (i.e. vector saturation operations and the like). But even so it is important to realize the limitations of this approach. Generally implementations of transcendental functions require platform specific optimizations to get the best performance and

Hi all. In fact, this is how we have implemented it in our compiler (intel's OpenCL). We have created a .bc file for every architecture. Each file contains all the SIMD versions for the functions to be vectorized. To cope with the massive amount of code to be produced, we implemented a dedicated tblgen BE for that purpose. We are willing to share that code with the llvm community, in case this

Thanks again for your help Steve, I’m thinking perhaps my “SelectADDRrr” pattern is inadequate. The sign-extension is at the hardware level, the code generator sees (should see) it as a 16-bit signed register value. My implementation is just: bool SHAVEISelDAGtoDAG::SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset) { if ((Addr.getOpcode() == ISD::ADD) { Base

I've no idea, but without it, the 'std::to_string' definitions are not enabled! -----Original Message----- From: Renato Golin [mailto:renato.golin at linaro.org] Sent: 06 July 2016 19:35 To: Martin.ORiordan at movidius.com Cc: LLVM Developers <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] GCC prerequisites for building LLVM head? On 6 July 2016 at 19:02, Martin J.

Thanks :) From: 陳韋任 [mailto:chenwj.cs97g at g2.nctu.edu.tw] Sent: 14 April 2017 12:53 To: Martin J. O'Riordan <martin.oriordan at movidius.com> Cc: LLVM Developers <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] Options for timing passes in LLVM? Refer to `llc` document [1], it would be `--time-passes`. [1] http://llvm.org/docs/CommandGuide/llc.html HTH,

I was investigating an error diagnostic in the following test example: typedef signed char char16 __attribute__((ext_vector_type(16))); void test( char16 srcA, char16 srcB, char16 *dst) { *dst = ( srcA == srcB ); } which produces the message: mismatch.c:5:10: error: assigning to 'char16' from incompatible type 'char __attribute__((ext_vector_type(16)))' *dst = (

Thanks Ahmed and also Alex for your replies. This is more or less what I was realising, but it is a great confidence booster to know that it is the correct way also. I can replace all of my various 'Select*' specialisations with version that use 'ReplaceNode/SelectCode' and return 'void', but what about the places where I currently call 'Select(N)' directly?

On Mon, Jun 26, 2017 at 5:04 AM, ORiordan, Martin <martin.oriordan at intel.com > wrote: > Thanks Sean and Silva. > > > > I guess what I was seeking was a URL that I could point (non-compiler) > people at, but I guess no such reference exists. What I can do if > reference bot the source manager and use ‘-mllvm -debug-pass=Structure’ > for each optimisation level,

Generally it is safer to include ISO headers first (using the ‘#include <...>’ form) so as to minimise the possibility that a later user declaration or macro definition interferes with the correctness of the Standard libraries. It also tends to make pre-compiled header implementations faster and more shareable across a larger set of files. I would like to suggest revising the LLVM

Sorry for the delay, I had to experiment and build everything to be sure. I am actually getting the same problem with GCC v4.9.3 on CentOS, but for both Cygwin and Linux adding '-D_GLIBCXX_USE_C99' to the '-DCMAKE_CXX_FLAGS:STRING=' flag during configuration cured the problem. MartinO -----Original Message----- From: Renato Golin [mailto:renato.golin at linaro.org] Sent: 06

Hi LLVM-Dev, I have just integrated the changes from top-of-tree at SVN #262824 (yesterday) having been previously at #262217 (a week ago). I am getting the following error for every instruction: CUSTOMBUILD : error : No schedule information for instruction 'FOOBAR' What has changed that would cause this and how can I fix it in my target? Thanks, MartinO

We have added our own proprietary target to LLVM and up until recently it was configured only for this target. I now build it to include additional targets and this all works fine, I just need to specify the associated triple when compiling and the correct code-generator is selected. But I would like to have it default to the triple for our processor when no triple is specified, and while I can

Hi LLVM and CLang Devs, At the moment my company (Movidius) is considering contributing the changes we have made to LLVM and CLang in order to support our proprietary processor, and I would like to seek advice on how best to approach doing this? I am pretty sure that there are coding guidelines and conventions that we should be following but have not followed over the course of the last few