similar to: [LLVMdev] [patch] alias instruction for Intel syntax

I'm trying to write a script for checking whether the compiler recursed properly. rkotler at mipsswbrd002:~/slave/recurse3be/build$ find . -name "*.o" -exec cmp '{}' ../../recurse2be/build/'{}' \; |& tee foo.txt Is anyone else doing this? There 2 compilers, recurse 2 and recurse3 that in principle should be identical. Obviously if there is date and time

On Oct 28, 2013, at 2:02 PM, Tyler Hardin <tghardin1 at catamount.wcu.edu> wrote: > See the source here: https://github.com/earl/llvm-mirror/blob/master/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp. It looks like getRegisterName might do what you want, but I don't know where it's coming from. (Whether it's a function or a member of a super class. Hopefully, if it's

See the source here: https://github.com/earl/llvm-mirror/blob/master/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp. It looks like getRegisterName might do what you want, but I don't know where it's coming from. (Whether it's a function or a member of a super class. Hopefully, if it's a member, it's public.) PS Sorry for the duplicate, Stephen. I forgot to CC the list. On

Can't you just include the generated files? What different way would you like them exposed? On Mon, Oct 28, 2013 at 11:23 AM, Stephen Checkoway <s at pahtak.org> wrote: > > On Oct 28, 2013, at 2:02 PM, Tyler Hardin <tghardin1 at catamount.wcu.edu> > wrote: > > > See the source here: >

I am considering using MipsInstPrinter::printAliasInstr, which is auto-generated in MipsGenAsmWriter.inc, to print assembly idioms defined as instruction aliases. For example, an instruction which used to be printed as "nor $1, $2, $zero" can be printed as "not $1, $2" This is nice because it makes the code printed by code-gen or disassembler more readable. However, the

Hello everyone, I'm a newbie of llvm. I'm trying to insert Intel MPX instruction BNDCU with BuildMI. I add my machinefunctionpass at addPreEmitPass2. Here is the code of insertion: BuildMI(MBB, MI, DL, TII->get(X86::BNDCU64rr)).addReg(X86::BND2, RegState::Define).addReg(X86::R10); And here is to stack track when I compiler program with modified llc:

On Jun 22, 2011, at 6:15 PM, Jim Grosbach wrote: > > On Jun 22, 2011, at 9:00 AM, Renato Golin wrote: > >> On 22 June 2011 16:50, Jim Grosbach <grosbach at apple.com> wrote: >>>> This sounds like a dead end as newer binutils are GPLv3. >>> >>> Yeah, that's definitely a very real concern and a big motivation to get the MC based asm parser

On Wed, Oct 09, 2013 at 08:06:42PM -0500, Jay Cornwall wrote: > Hi, > > This patch adds R600/SI disassembly text to compiled object files, when > a code dump is requested, to assist debugging in Mesa clients. > > Here's an example of the output in a Mesa client with a corresponding > patch and RADEON_DUMP_SHADERS set: > > Shader Disassembly: > >

On Jun 22, 2011, at 10:03 AM, Damjan Marion wrote: > > On Jun 22, 2011, at 6:15 PM, Jim Grosbach wrote: > >> >> On Jun 22, 2011, at 9:00 AM, Renato Golin wrote: >> >>> On 22 June 2011 16:50, Jim Grosbach <grosbach at apple.com> wrote: >>>>> This sounds like a dead end as newer binutils are GPLv3. >>>> >>>> Yeah,

I have a question regarding implementation of subclasses of MCInstPrinter. I am implementing Machine IR layer to MC layer lowering for Mips. What's the best way to print the value of "Register" in the following code in MCAsmStreamer::EmitRegisterName? Do I have to convert the LLVM register number back to its corresponding dwarf register number in function

I'm iterating over MCInsts and I'd like to examine particular instructions. For example, I'd like to look at all x86 CALL64m instructions. I may be missing something, but it seems like my only option is to use MCInstPrinter::getOpcodeName and compare strings. (Of course, I could iterate through the opcodes and build up a table of the ones I'm interested in to avoid string

> On Oct 1, 2018, at 3:25 PM, David Blaikie <dblaikie at gmail.com> wrote: > > > On Mon, Oct 1, 2018 at 3:24 PM JF Bastien <jfbastien at apple.com <mailto:jfbastien at apple.com>> wrote: >> On Oct 1, 2018, at 3:16 PM, David Blaikie <dblaikie at gmail.com <mailto:dblaikie at gmail.com>> wrote: >> >> (my vote, somewhat biased - is that

> On Oct 1, 2018, at 3:16 PM, David Blaikie <dblaikie at gmail.com> wrote: > > (my vote, somewhat biased - is that I'd love to see more investment in Bloaty (to keep all these sort of size analysis tools and tricks in one place), but sort of accept folks are probably going to keep building more infrastructure for this sort of thing in LLVM directly) I get where that comes

Hello, I worked on a code size analysis tool for a 'week of code' project and think that it might be useful enough to upstream. The tool is inspired by bloaty (https://github.com/google/bloaty), but tries to do more to attribute code size in actionable ways. For example, it can calculate how many bytes inlined instances of a function added to a binary. In its diff mode, it can show how

Hi In my MC6809 backend, in llvm/lib/Target/MC6809/InstPrinter/MC6809InstPrinter.cpp, I have the routine void MC6809InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); ZZ if (Op.isImm()) { int64_t Imm = Op.getImm() + 2; <<<======================== O << "$"; if (Imm

Hi, I'm from Intel compiler department. I am proposing the integration of a backend targeting Nios II processor architecture. Nios II is a 32-bit general-purpose RISC processor core designed specifically for the Altera family of FPGAs. All information at about Nios II can be found at Altera website https://www.altera.com/products/processors/support.html, including the current ISA

Hi, Have anybody recently built LLVM in Debug mode /within/ space requirements from the Getting Started doc? https://llvm.org/docs/GettingStarted.html#hardware > An LLVM-only build will need about 1-3 GB of space. A full build of LLVM and Clang will need around 15-20 GB of disk space. From my experience this numbers looks drastically low. On FreeBSD my recent builds consumed more than

Hi, I'd like to modify MachineBasicBlock contents within a MachineFunctionPass on the basis of how many CPU cycles the assembly instructions corresponding to the MBB take. I'm using the AVR backend and the number of CPU cycles every AVR assembly operation takes is openly available. Is there any straightforward way of getting the opcode mnemonics corresponding to a MachineInstr? I've

On Tue, Mar 17, 2015 at 6:14 PM, Tim Northover <t.p.northover at gmail.com> wrote: >> As a simplification, the compiler deals almost exclusively in pseudo >> instructions. By x86 analogy, using pseudos to unfold a TEST32rm into >> MOV32rm + TEST32rr means I can skip the complex operand fitting effort >> needed to pick specific machine instructions. There are many

I am trying to do the following pseudo-to-real instruction conversion: PseudoMFHI GPR32:$rd, ACC64:$ac -> MFHI GPR32:$rd Is there a way to tell the assembler, disassembler and instprinter to ignore the ACC64:$ac operand? I know I can use PseudoInstExpansion to accomplish this, but I just thought it would be convenient to have a flag for this, something like flag "DisableEncoding".