similar to: [LLVMdev] MCInst uniqueness

Cool. I've almost done the disassembly part. Any hint on how to translate from MCInst to ELF binary? E.g., which LLVM tool to use? I only find tools effective on LLVM Bitcode. Thanks so much again. On Wed, Sep 18, 2013 at 7:48 PM, James Courtier-Dutton < james.dutton at gmail.com> wrote: > How about: > http://blog.llvm.org/2010/01/x86-disassembler.html > > This is what

The MCInstrDesc has a method getNumDefs() which tells you how many 'out registers' that MCInst has. The 'out' registers are always at the beginning of the list. You can also use getNumOperands(). Not sure if this is what you are looking for. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Vladimir Pouzanov

Hi, By way of example, I have the following instruction: 44 8b 80 c8 03 00 00 movl 968(%rax), %r8d 1) How is this represented in MCInst? 2) Is there information in MCInst that would tell me which bytes of the instruction are responsible for the 968? The reason I am asking is that I want to work with the bytes disassembled/decoded to an instruction at MCInst level.

Hi, Am Mittwoch, 26. Dezember 2012, 15:20:27 schrieb Manny Ko: > The MCInstrDesc has a method getNumDefs() which tells you how many 'out > registers' that MCInst has. The 'out' registers are always at the beginning > of the list. You can also use getNumOperands(). I've run into the problem, that this doesn't work for instructions which have variadic arguments

Hi all. I'm looking for some way to do code analysis with LLVM. Can someone please give me a hint, if it is possible to query an MCInst for what are input operands and what are output operands? Small example. Consider we have an instruction: str r1, [sp, #8] Being mapped into MCInst instance it has the following operands: <MCOperand Reg:61> <-- maps to reg r1

The attached patch includes no test-case and isn't consistent with the rest of the file: - constants should be on the right hand side of comparisons - the braces around your single line 'if' aren't needed. On Sun, Sep 15, 2013 at 2:39 PM, James Courtier-Dutton < james.dutton at gmail.com> wrote: > I attach a patch that fixes this bug. Applies to llvm 3.4svn > >

Test case attached. It is not a test case that works within the llvm test-suite yet, but it does demonstrate the problem. I would like some advice on how to modify this test_case so that it can be added to the automated llvm test cases. On 15 September 2013 23:02, David Majnemer <david.majnemer at gmail.com> wrote: > The attached patch includes no test-case and isn't consistent

Hi, I am looking at the "LLVMOpInfoCallback GetOpInfo" callback. Example 1 GOOD: 41 c6 84 24 16 04 00 00 0c : movb $12, 1046(%r12) Makes calls to the callback with: Offset = 0x4, Size = 0x4 <- Octets: 16 04 00 00 Offset = 0x8, Size = 0x1 <- Octets: 0c That was correct. Example 2 BAD: c7 45 98 a1 ff ff ff : movl $4294967201, -104(%rbp) Makes calls to the callback

I attach a patch that fixes this bug. Applies to llvm 3.4svn Please commit it please. Kind Regards James On 13 September 2013 17:46, James Courtier-Dutton <james.dutton at gmail.com>wrote: > Hi, > > I am looking at the "LLVMOpInfoCallback GetOpInfo" callback. > > Example 1 GOOD: > 41 c6 84 24 16 04 00 00 0c : movb $12, 1046(%r12) > > Makes

On Jul 9, 2009, at 5:34 PM, David Greene wrote: > Can someone explain what MCInst is vs. MachineIntr? Sure. MCInst is designed to be part of the "MC" set of libraries, which is stuff dealing with machine code. We're building a suite of assemblers and disassemblers out of this. MCInst is integral to this plan. For an assembler you have two pieces: 1. "Recognize"

On Friday 10 July 2009 00:19, Chris Lattner wrote: > asmprinter::printInstruction will lower a MachineInstr to an MCInst, > then call the MCInst asmprinter to do the hard formatting work. You > can see a horrible simple skeleton of this idea in > X86ATTAsmPrinter::printMachineInstruction. Yep, that's where I hit the problem. I'm patching the sources for the comment emitter

Dear All, I am following a flow to generate object files(.o) from input (.s assembly) files. The input .s is given to AsmParser, which creates MCInst after matching instruction opcode. These MCInst are converted to MCStream and then finally emitting to an object file using Target Code Emitter. I am considering whether hazard recognition can be done on the list of MCInst, which I get after

Mario, On Nov 29, 2012, at 3:00 PM, Mario Guerra <mariog at codeaurora.org> wrote: > We're developing an integrated assembler for a VLIW target, and some of the > optimizing our assembler needs to do must be done on a per-packet basis. > This requires us to be able to traverse instruction within a packet, and one > particular optimization requires traversal of previous

Hi, Dear LLVM Dev Group, I am doing an LLVM project aimed to disassemble an ARM ELF binary executable to the MCInst format, inserting some instructions or doing some modification, and re-assemble the MCInst to an ELF binary. As I used the llvm-mc, it seems to only have the option "llvm-mc -disassemble", which reads strings and output strings. Is there any command or function that can

Mario, On Nov 29, 2012, at 4:04 PM, Mario Guerra <mariog at codeaurora.org> wrote: > Thanks for your reply. This is actually one approach we are considering, but > there are a few issues with it we weren't sure how to address. > > One is that the lifespan of an MCInst seems to be limited to the scope of > AsmPrinter, and we need them to be persistent in order to do a

Hello Owen, > There should already be sufficient support for what you're trying to do. See > MCOperand::CreateInst(). The concept is that you'll build a composite MCInst in > your AsmPrinter::EmitInstruction() method, which uses Inst-type MCOperands to > hold a list of sub-instructions. Then you call AsmStreamer::EmitInstruction() on the > composite MCInst. Thanks for

On Mon, 6 May 2019 at 10:13, James Courtier-Dutton via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Although the above is mentioning bytes, looking at the "/ 8" and "& 0x7" makes it look like the author meant octets and not bytes. > Bytes can be any size of bits. I don't think you'll have much luck trying to make that stick for a general audience,

Can someone explain what MCInst is vs. MachineIntr? I'm porting some patches we have here that affect MachineInstrs and am wondering whether I need to make similar changes in MCInst. Why do we have two machine instruction representations? -Dave

On Thu, Nov 29, 2012 at 3:00 PM, Mario Guerra <mariog at codeaurora.org> wrote: > Hello all, > > We're developing an integrated assembler for a VLIW target, and some of the > optimizing our assembler needs to do must be done on a per-packet basis. > This requires us to be able to traverse instruction within a packet, and one > particular optimization requires traversal

Hi James, Not sure if you've already found the problem but I've been looking at this issue a bit as a way to learn. What I've seen is that the wrong operand names are used for the instruction which causes the decoder emitter to fail to recognize the operands. The attached patch changes the names of the operands and adds a test for the disassembly of the instruction. I haven't