similar to: [LLVMdev] ARM integrated assembler - unknown directive errors

Hi, > arm-linux-clang > -Iarm-2013.05-24-arm-none-linux/arm-none-linux-gnueabi/libc/usr/include > -integrated-as -msoft-float -save-temps -O3 -mcpu=cortex-a8 -c -o test.o > test.c Hmm. It looks like save-temps is interfering with integrated-as. What's happening is that Clang is quite capable of taking those directives from CodeGen and putting them in an object file (the normal

On Feb 17, 2011, at 10:35 PM, Вадим Марковцев wrote: > Hello everyone, > > I've added the "S" suffixed versions of ARM and Thumb2 instructions to tablegen. Those are, for example, "movs" or "muls". > Of course, some instructions have already had their twins, such as add/adds, and I leaved them untouched. Adding separate "s" instructions is

Hi Jim, On Tue, Sep 25, 2012 at 10:52:58AM -0700, Jim Grosbach wrote: > These errors are from the assembler, not LLVM. Specifically, your binutils is > too old. Given that it doesn't even recognize the ".syntax" directive, they're > *very* much too old. You need to upgrade. > -Jim She said in her previous mail, P.S. Because I got error when I use

Hello everyone, I've added the "S" suffixed versions of ARM and Thumb2 instructions to tablegen. Those are, for example, "movs" or "muls". Of course, some instructions have already had their twins, such as add/adds, and I leaved them untouched. Besides, I propose the codegen optimization based on them, which removes the redundant comparison in patterns like orr

Dear list, git checkout llvmorg-8.0.0 -b llvm8.0 cmake -G "Unix Makefiles" ../llvm-project/llvm -DCMAKE_BUILD_TYPE=Debug -DLLVM_ENABLE_PROJECTS="clang;lld" -DLLVM_TARGETS_TO_BUILD="X86;NVPTX;AMDGPU;ARM;AArch64" [arm.cpp] #define vst4_lane_f16(__p0, __p1, __p2) __extension__ ({ \ float16x4x4_t __s1 = __p1; \ __builtin_neon_vst4_lane_v(__p0, __s1.val[0],

Hi, I do not get your result. Do I miss something? $COMP_ROOT/clang++ --target=arm-arm-eabihf -march=armv8.2a+fp16 arm.cpp -S -o - -O3 .text .syntax unified .eabi_attribute 67, "2.09" .eabi_attribute 6, 14 .eabi_attribute 7, 65 .eabi_attribute 8, 1 .eabi_attribute 9, 2 .fpu crypto-neon-fp-armv8 .eabi_attribute 12, 4

Hi, I wanted to know if it was possible to force ARM backend to compile a function in ARM while the rest is in Thumb mode. I tried the attributes which is used in GCC but it doesn't work. Here is what I tried: https://pastebin.com/jCr5LPUY Thanks in advance, Uvekilledkenny -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi Andrea, That is because the LR is the fixed register as per the http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042e/IHI0042E_aapcs.pdf and out_char() function is not the leaf function ,Hence compiler tends to save and restore the LR and the save and restore of register r11 is to align stack for 8 bytes as per ARM EABI. Thanks ~Umesh On Tuesday, October 15, 2013, Umesh Kalappa

Dear all I use arm-linux-gcc 2.95.2, because the code generated by version 3.X and 4.X can not run on SimpleScalar. So I use the arm-linux-gcc 2.95.2 *only*, the version is recommended by SimpleScalar. The code generated by arm-linux-gcc 2.95.2 can run on SimpleScalar. Now I want to use llvm/clang to generate ARM assembly code and arm-linux-gcc 2.95.2 to be assembler. Unfortunately, I got some

Simplescalar is not compatible with llvm because the binutils simplescalar is based on is ancient. Jim On Sep 26, 2012, at 12:21 AM, 陳奕梅 <ymchen at sslab.cs.nctu.edu.tw> wrote: > Dear all > > I use arm-linux-gcc 2.95.2, because the code generated by version 3.X and 4.X can not run on SimpleScalar. > So I use the arm-linux-gcc 2.95.2 *only*, the version is recommended by

I'm trying to find a way to emulate a floating point instruction, say a floating point add. My understanding is that in order to do that I need to execute setOperationAction(ISD::FADD, (MVT::f32, Expand); setOperationAction(ISD::FADD, (MVT::f64, Expand); in MyTargetISelLowering.cpp, MyTargetLowering::MyTargetLowering(...). However for some reason I'm still seeing a floating point add in

Hi andrea, R11 treated as frame pointer at arm backend , which is fixed again . Thanks Umesh On Tuesday, October 15, 2013, Andrea Mucignat <andrea at nestlabs.com> wrote: > Umesh, > Makes some sort of sense to me, OTOH: > If instead of choosing r11 as a "dummy" to align the stack we had chosen some other register in the range r0-r7 then we could have emitted the PUSH

Umesh, Makes some sort of sense to me, OTOH: If instead of choosing r11 as a "dummy" to align the stack we had chosen some other register in the range r0-r7 then we could have emitted the PUSH encoding T1 (2 bytes opcode) as opposed to the encoding T2 (which is a 4 bytes opcode). A On Tue, Oct 15, 2013 at 2:59 AM, Umesh Kalappa <umesh.kalappa0 at gmail.com>wrote: > Hi

On 10 September 2010 04:47, Liu <proljc at gmail.com> wrote: > trying this: > clang -march=armv7-a -mcpu=cortex-a9 -ccc-host-triple > arm-none-linux -ccc-gcc-name arm-none-linux-gnueabi-gcc a.c Hi Liu, That doesn't work for me. $ clang -march=armv7-a -mcpu=cortex-a9 -ccc-host-triple arm-none-linux -ccc-gcc-name arm-none-linux-gnueabi-gcc alias.c clang: warning: unknown

trying this: clang -march=armv7-a -mcpu=cortex-a9 -ccc-host-triple arm-none-linux -ccc-gcc-name arm-none-linux-gnueabi-gcc a.c 2010/9/10 Emmanuel Blot <eblot.ml at gmail.com>: > Hello, > > Is there a quick tutorial to build the LLVM toolchain from a Linux or > Mac OS X x86 host for an ARM v4/v5/v6 ELF target? > It this configuration supported, and is it possible to build the

On 26 November 2013 18:13, Tim Northover <t.p.northover at gmail.com> wrote: > Do you remember what those features are Renato? MC has been around > years, we really should start sorting them now. > No. I remember there were issues, but I never catalogued them. I agree we should move as soon as possible, and there's nothing holding me of doing it. I think post-3.4 we can cope

>> Out of curiosity, can't clang do the assembly itself in this case? > > It can, but you need to use -integrated-as, because that's not the default > yet. (some missing features). Do you remember what those features are Renato? MC has been around years, we really should start sorting them now. Cheers. Tim

Hello, Is there a quick tutorial to build the LLVM toolchain from a Linux or Mac OS X x86 host for an ARM v4/v5/v6 ELF target? It this configuration supported, and is it possible to build the Clang compiler for this host/target combination? I know about the installation page, but I keep failing to build this toolchain with LLVM 2.7. Maybe it is not (yet) supported? Thanks, Manu

On 5 February 2013 23:21, Greg Fitzgerald <garious at gmail.com> wrote: > > Is this for inline asm? > > Yep > In that case, using GAS is always a better options... for now. ;) What I'd prefer to see is if the integrated-as doesn't recognize the > option, clang should report a warning and switch to the 'no-integrated-as' > path. Thoughts? > The

Hello, I want to compile MiBench by clang, and the target-ISA is armv4. The code generated using llvm-2.9, clang-2.9, and arm-linux-gcc (gcc version 2.95.2), simulator is sim-panalyzer 2.0.3 . I use these commends: $ clang -O3 -o hello.ll -c -emit-llvm hello.c $ llc -O3 -o hello.s -march=arm -mcpu=strongarm1100 hello.ll $ arm-linux-gcc -O3 -march=armv4 -mcpu=strongarm1100 -static