similar to: [LLVMdev] LLVM Disassembler question

i want to emit binary code for the following implemented vector assembly instructions. P_256B_LOAD_DWORD R_0_R2048b_0, pword ptr [rip + b] P_256B_LOAD_DWORD R_0_R2048b_1, pword ptr [rip + c] P_256B_VADD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_0 P_256B_STORE_DWORD pword ptr [rip + a], R_0_R2048b_0 I added the following lines in X86MCInstLower.cpp; unsigned NewOpc; switch (OutMI.getOpcode())

This attempts to address http://llvm.org/bugs/show_bug.cgi?id=18220 It also fixes a test which was requiring the *wrong* output. I'm relatively happy with this part, and it even solves most of the hard part of feature request for .code16 in bug 8684 — which was actually why I started prodding at this. But I could do with some help with the 16-bit signed relocation handling, which I've

I was away doing other things for a while, but I have an API patch separated out, which (in addition to being much smaller than past megapatches) corrects two issues Chris identified in his most recent set of patches: - First, it makes the API a good deal simpler. Now, you can instantiate a single MCDisassembler and, each time you want an instruction disassembled, you can simply pass

On 06/25/2013 04:46 PM, Jim Grosbach wrote: > Hi Sid, > > This feels like it’s exposing too much of the disassembler internals > into the MCOperand representation. I’m not sure I follow why that’s > necessary. Can you elaborate a bit? > A packet contains 1-4 insns and until the contents of the entire packet are known the meaning of any individual insn is not known with 100%

That depends on how you define "one ARM instruction." It's not a clear cut thing. For example, is "add r1, r2, r3" the same ARM instruction as "add r1, r2, #4"? What is a distinct instruction and what's a variant encoding of the same instruction is often entirely a matter of convenience. -Jim On Jun 8, 2012, at 6:40 AM, Fan Dawei <fandawei.s at

Hi, My apologies if this appears to be a very trivial question -- I have tried to solve this on my own and I am stuck. Any assistance that could be provided would be immensely appreciated. What is the absolute bare minimum that I need to do to disassemble an array of, say, ARM machine code bytes? Or an array of Thumb machine code bytes? For example, I might have an array of unsigned chars -- how

Hi James, On Aug 12, 2011, at 1:02 AM, James Molloy wrote: > I’ve got a load of examples for this, but I’ll pick one. > > echo '0xB0 0x00 0x00 0x00' |/work/llvm-cmake2/build/bin/llvm-mc -arch arm --disassemble – > strheq r0, [r0], -r0 > > This instruction encoding is marked UNPREDICTABLE. The question is: does a disassembly of it have value? One use case put

I'm working on a disassembler for hexagon (vliw) architecture and I would like to add an additional operand type, "kAux" to the MCOperand class. The reason for this is that each insn has parse bits which are not explicit operands and have differing meanings based on the insn's location within the packet and the number of insns inside the packet. In order for the disassembler

Hi Jim, Thanks for reply. I'm sorry I didn't make myself clear enough. The MCInst created by MCDisassembler depends on the instructions defined in td files. These instructions do not have a one to one mapping to ARM instructions. There are usually one or more instructions defined in the td file correspond to one actual ARM instruction. Thanks, David On Thu, Jun 7, 2012 at 1:27 PM, Jim

Hi Sid, This feels like it’s exposing too much of the disassembler internals into the MCOperand representation. I’m not sure I follow why that’s necessary. Can you elaborate a bit? -Jim On Jun 25, 2013, at 8:24 AM, Sid Manning <sidneym at codeaurora.org> wrote: > > I'm working on a disassembler for hexagon (vliw) architecture and I would like to add an additional operand type,

Hi Aiden, The easiest thing I can do is to point you to the source of the "llvm-mc" tool, which does exactly what you ask in its "-disassemble" mode. The code is rather small, so it should be easy to work out. tools/llvm-mc Cheers, James -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Aidan Steele Sent:

Bill, thanks for your comments. I'll respond to them individually. I've attached a new revision of the patch that addresses them. Patch built and tested against SVN 79487, with the additional attached fix that fixes an Intel table bug. Sean On 2009/08/18, at 0:57, Bill Wendling wrote: > 0. Watch out for tabs! Fixed. Thanks. > 1. Includes like this "#include

The attached patch includes no test-case and isn't consistent with the rest of the file: - constants should be on the right hand side of comparisons - the braces around your single line 'if' aren't needed. On Sun, Sep 15, 2013 at 2:39 PM, James Courtier-Dutton < james.dutton at gmail.com> wrote: > I attach a patch that fixes this bug. Applies to llvm 3.4svn > >

On Aug 19, 2009, at 4:39 PM, Sean Callanan wrote: > thanks for your comments. I'll respond to them individually. I've > attached a new revision of the patch that addresses them. Patch > built and tested against SVN 79487, with the additional attached fix > that fixes an Intel table bug. Thanks Sean, comments below. Are you sure you attached the updated patch? I

On Jun 7, 2012, at 7:53 AM, Fan Dawei <fandawei.s at gmail.com> wrote: > Hi Tim, > > Thanks a lot for your help! I'm very grateful. > > libc.so is a prelinked library, I'll build a non-prelinked one and have another try. > > I'm now at the start of a binary translation project. I want to convert ARM binary code [*] to llvm ir, which is then translated to

Test case attached. It is not a test case that works within the llvm test-suite yet, but it does demonstrate the problem. I would like some advice on how to modify this test_case so that it can be added to the automated llvm test cases. On 15 September 2013 23:02, David Majnemer <david.majnemer at gmail.com> wrote: > The attached patch includes no test-case and isn't consistent

Hi, I am looking at the "LLVMOpInfoCallback GetOpInfo" callback. Example 1 GOOD: 41 c6 84 24 16 04 00 00 0c : movb $12, 1046(%r12) Makes calls to the callback with: Offset = 0x4, Size = 0x4 <- Octets: 16 04 00 00 Offset = 0x8, Size = 0x1 <- Octets: 0c That was correct. Example 2 BAD: c7 45 98 a1 ff ff ff : movl $4294967201, -104(%rbp) Makes calls to the callback

> But where is the flat set? Maybe I can debug and check what is going on. The MCInstrDesc are in a table in lib/Target/PowerPC/PPCGenInstrInfo.inc of your build directory. > Some additional information: > > MCInst opcode: 0x7cb > Decode Index: 0x1e I had assumed this would have dissembled to '// Inst #234 = BC' which does have the branch flag set, but I think that

Hi Sean, > the attached diff implements a table-driven disassembler for the X86 > architecture (16-, 32-, and 64-bit incarnations), integrated into > the MC framework. The disassembler is table-driven, using a custom > TableGen backend to generate hierarchical tables optimized for fast > decode. The disassembler consumes MemoryObjects and produces arrays > of

I attach a patch that fixes this bug. Applies to llvm 3.4svn Please commit it please. Kind Regards James On 13 September 2013 17:46, James Courtier-Dutton <james.dutton at gmail.com>wrote: > Hi, > > I am looking at the "LLVMOpInfoCallback GetOpInfo" callback. > > Example 1 GOOD: > 41 c6 84 24 16 04 00 00 0c : movb $12, 1046(%r12) > > Makes