similar to: [LLVMdev] Inserting C++ code on tablegen to improve code generation statistics

Hi all, I have attached the complete test suite. it has different directories for gcc, llvm-gcc , clang and lli-clang. Source code , makefile and run script (contains number of times the program should execute) for each case are available inside each directory. * FOLLOWING ARE THE STATISTICS WHILE USING LLI FOR SINGLE ITERATION*

On Sep 17, 2013, at 5:15 AM, Leandro Santiago <leandrosansilva at gmail.com> wrote: > Hello to all. I'm trying to implement a simple register allocator using graph colouring (I know, everyone has already done that :-)) and I'm also using LLVM 3.4 from master branch. > > The algorithm I'm using is based on the one described on the "Modern Compiler Implementation in

On Nov 14, 2009, at 11:52 PM, Prasanth J wrote: > step 4: > running monolith.bc for 10000 iterations using lli tool and measured the time. How are you doing this? -eric

Hi Hal, Yes, you could definitely expand them later. Custom inserters are effectively just a very early expand pseudo instruction. You can even expand them very late in the MC lowering (asmprinter) if you really need to. That could get tricky, as you'll effectively be fibbing to the register allocator. ARM uses quite a lot of late expanded pseudo-instructions, for example, though generally

Hi, While investigating a performance issue with an internal codebase I came across what looks to be poor register allocation. I have constructed a small(ish) reproducible which demonstrates the issue (see test.ll attached). I have spent some time going through the register allocator to understand what is happening. I have also experimented with some small changes to try and improve the

Thanks again. One more question here: Since the regalloc works once per function, do I stil have access to the Call graph? Just saving information between regalloc passes for different functions may not be enough for my case. I will need to maintain the regalloc info of various passes in the call graph order. Anyways thanks for your inputs. I will get back if I need to learn more. Sanjiv On Nov

I managed to link my RegAlloc.a library to llc tool but can;t make the same with lli tool. Should I use USEDLIBS variable in lli makefile (like llc) or there is another way? On 8/20/06, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Dear Anton, > > you can add your register allocator strait iin the > "lib/CodeGen/Passes.cpp", and then

Hi Kristof, Thanks for the measurements. > On May 24, 2017, at 6:00 AM, Kristof Beyls <kristof.beyls at arm.com> wrote: > >> >> On 23 May 2017, at 21:48, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> Great! >> I thought I had to look at our pipeline at O0 to make sure optimized regalloc was

Dear Anton, you can add your register allocator strait iin the "lib/CodeGen/Passes.cpp", and then 're-make' it: "makellvm llc", on the top of lib/CodeGen. It is faster than running make from LLVMOBJDIR. The problem is that it only add to llc the changes on the lib/CodeGen directory. If you change other parts, a make from LLVMOBJDIR will synchronize it. Try adding

Hi, again, I think you can do it in the same way that the other allocators have been coded, i.e extend RA, register the pass and so forth. I am not sure about the best way to pass information among a run of RegAlloc to the other, maybe the other guys in the list could suggest something. Yet, you can always dump it into a file, and read it again, everytime it is necessary. Remember that

At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level

Hi LLVM, I ran into a case where RegAlloc would insert a spill across instruction that had same register for output operand and implicit-def. The effect this had was that spill code would immediately overwrite the output result. Is this the expected result of setting up MyInst this way? In other words, does RegAlloc know to not insert spill in case it sees that output reg is same as one of

On May 24, 2011, at 8:22 AM, Jonas Paulsson wrote: > Hi (Jakob), > > in reference to the prior message below, I have the following follow-up questions, as I also need a scheduling pass > prior to regalloc. I need to do this in order to set VLIW-flags, so that the RA is aware of several MI's > per cycle with a redefined LiveRange::overlap-function. On a multiple-issue cycle, a

Hi again! I've managed to run the llvm-test with the options Fernando told. What I did was the following: I changed llc regalloc option in TEST.llc.makefile to my allocator. I changed LLCBETAOPTION in makefile.programs file for all architechtures to use my allocator. I run make TEST=nightly report.html and got all tests under LLCBETA failed ('*' symbol). Though I know that my

Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probable reason of this error is that no LiveInterval information for newly MBB which is used by Register Allocation. And, LiveIntervals depend

Hello to all. I'm trying to implement a simple register allocator using graph colouring (I know, everyone has already done that :-)) and I'm also using LLVM 3.4 from master branch. The algorithm I'm using is based on the one described on the "Modern Compiler Implementation in C". My implementation is totally experimental and doesn't aim to be fast, eficient or even

Hello Jakob, I think I've found something interesting that may help you get a better idea of what's going on. While looking at the debug info I noticed that the coalescer was removing lots of copies that could help the allocator make more cross class copies. As a test, I disabled the join-liveintervals option in the coalescer which gave me the surprise of making the regalloc succeed. To

Great! I thought I had to look at our pipeline at O0 to make sure optimized regalloc was supported (https://bugs.llvm.org/show_bug.cgi?id=33022 <https://bugs.llvm.org/show_bug.cgi?id=33022> in mind). Glad I was wrong, it saves me some time. > On May 22, 2017, at 12:51 AM, Kristof Beyls <kristof.beyls at arm.com> wrote: > > >> On 22 May 2017, at 09:09, Diana Picus

Hi Kristof, Thanks for going back so fast! > On May 24, 2017, at 12:57 PM, Kristof Beyls <kristof.beyls at arm.com> wrote: > >> >> On 24 May 2017, at 19:31, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> Hi Kristof, >> >> Thanks for the measurements. >> >>> On May 24, 2017, at

Hi Quentin, MyInst is a custom instruction that has implicit-defs of fixed registers. The implicit-defs are seen at the end of Instruction Selection. I'd like to add a report, but I am working on an out-of-tree backend based on 7.0. I can try to help reduce the testcase down. Filed https://bugs.llvm.org/show_bug.cgi?id=41790 Regards, Kevin On 2019-05-07 3:45 p.m., Quentin Colombet wrote: