Displaying 20 results from an estimated 4000 matches similar to: "[LLVMdev] tablegen question"
2013 Aug 07
0
[LLVMdev] tablegen question
Why not just run the c preprocessor before running tablegen?
Micah
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Jeroen Dobbelaere
> Sent: Wednesday, August 07, 2013 1:33 AM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] tablegen question
>
> Hi,
>
> I am trying to make my tablegen
2017 Feb 15
4
Unsigned int displaying as negative
I see. If I put simm16 and immSExt16x in place of uimm16 and immZExt16x
respectively, the imm matches but it prints out -32768 (which is invalid
for sub16u). We are using uimm16 not match unsigned but for PrintMethod,
effectively uimm16 and simm16 are both Operand<i16>. I'm still unclear why
simm16 matches and uimm16 does not. Here is the pattern if that helps at
all.
So just as a
2019 May 20
2
GlobalISel: Very limited pattern matching?
> On May 20, 2019, at 10:04, Quentin Colombet <qcolombet at apple.com> wrote:
>
> +gisel folks
>
> Hi Alex,
>
> You’re doing the right thing.
> That’s a known limitation that we’ve discussed in https://reviews.llvm.org/D59227 <https://reviews.llvm.org/D59227> but we didn’t really reach a conclusion back them.
> Short term, I believe you’re right, we should
2013 May 30
2
[LLVMdev] How to associate extra comments to a MachineInstruction ?
> From: Eric Christopher
> Subject: Re: [LLVMdev] How to associate extra comments to a
> MachineInstruction ?
>
> Should be spelled like this yes?
>
> Asm->OutStreamer.AddComment("foo")
> Asm->EmitFoo();
>
> -eric
That should work at the moment that you are emitting the instructions.
But what would you do when you are manipulating a
2020 Jan 22
2
Inlining + CSE + restrict pointers == funtimes
Ok I think we have some common ground - CSE should choose the aliased
pointer over the non-aliased one because we don't want the no-aliasing
information to creep outwards from the inlined callsite.
I'll put together a patch in the coming days and add y'all as reviewers so
you get visibility.
Cheers,
-Neil.
On Wed, Jan 22, 2020 at 4:47 PM Jeroen Dobbelaere <
Jeroen.Dobbelaere at
2017 Feb 15
5
Unsigned int displaying as negative
Where does the unsignedSub come from?
On 2017-02-15 20:38, Ryan Taylor wrote:
> Sorry, it should be:
>
> defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs,
> GPRRegs, DSTRegs, i16, i16, i16, uimm16, immZExt16x>;
>
> On Wed, Feb 15, 2017 at 2:37 PM, Ryan Taylor <ryta1203 at gmail.com>
> wrote:
>
>> I see. If I put simm16 and
2020 Sep 29
5
restrict func param losing noalias when inlined
Johannes,
Thanks, I have been following along some of the thread(s) and the phab
reviews. The scope of this work is more encompassing than our current needs
and I've looked at trying to carve a piece out.
It's not clear to me what purpose the llvm.noalias intrinsic serves right
now. Also, if a mem instruction has !noalias metadata, then it should not
be aliased, but I must be missing
2020 Feb 20
2
Given one restrict pointer based on another, should they never alias?
Thanks, Jeroen, that really helps.
A follow-up question, if you don't mind. What if we have code somewhat
similar to your example in assign3() but it's in C++ and the pointer
derived from x is stored in a class member field:
class S {
public:
S(int *d): data(d) {}
int *getData() { return data; }
private:
int *__restrict__ data;
};
void assign4(int *pA, long N) {
int
2020 May 18
4
LLVM Alias Analysis Technical Call - Doodle Poll
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2020 May 21
2
LLVM Alias Analysis Technical Call - Doodle Poll
Great, thanks!
Are you planning on just talking about these things with slides? Do we have other things to which we can link for people to read?
-Hal
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory
________________________________
From: Tarique Islam <tislam at ca.ibm.com>
Sent: Thursday, May 21, 2020 8:19:31 AM
To:
2013 May 30
2
[LLVMdev] How to associate extra comments to a MachineInstruction ?
Hi,
is there a convenient way to associate/add a comment to a MachineInstruction, so that
in the produced assembly file, the comment is added next to the instruction ?
Greetings,
Jeroen Dobbelaere
2020 Jun 24
4
LLVM Alias Analysis Technical Call - New Doodle Poll
Hi, everyone,
We had a great call last month, and progress is definitely being made on several fronts. The notes from our last call are available here:
https://docs.google.com/document/d/1ybwEKDVtIbhIhK50qYtwKsL50K-NvB6LfuBsfepBZ9Y/edit#heading=h.vpxs8lkuxy79
and, also, pasted below.
DOODLE POLL:
As we discussed on our last call, I would like to schedule a regular call to discuss
2013 May 30
0
[LLVMdev] How to associate extra comments to a MachineInstruction ?
On Thu, May 30, 2013 at 2:16 PM, Jeroen Dobbelaere
<Jeroen.Dobbelaere at synopsys.com> wrote:
>> From: Eric Christopher
>> Subject: Re: [LLVMdev] How to associate extra comments to a
>> MachineInstruction ?
>>
>> Should be spelled like this yes?
>>
>> Asm->OutStreamer.AddComment("foo")
>> Asm->EmitFoo();
>>
>> -eric
2020 Feb 05
3
IndVarSimplify: getBackedgeTakenCount and Release vs Assert
Hi,
I am investigating a difference in code generation between release and assert builds of llvm.
The culprit is IndVarSimplify that comes up with different behavior on the same input:
in the assertion build, it does do an extra 'INDVARS: Rewriting loop exit condition'
After digging around, it seems that following change is the culprit:
-----
Author: Philip Reames <listmail at
2014 Apr 03
5
[LLVMdev] 32bit pointers on a (pure) 64bit architecture
Hi,
I am trying to get llvm working for an architecture that has 64bit
registers, but 32bit addresses.
Because of that, I want the pointers to also be 32bit, although they will
live in a 64 bit register.
On the frontend, I do not encounter any issues, but when I provide a
...
"p:32:32:32"
...
DataLayout specification to the backend, things get ugly:
- SelectionDag is producing a
2020 May 13
2
LLVM Alias Analysis Technical Call - Doodle Poll
Hi, everyone,
We've had a number of discussions recently, including on the Flang technical call, about potential improvements to LLVM's alias analysis to support handling restrict and restrict-like semantics.
We would like to try having a call to discuss these issues further. Please, if you're interested in joining, indicate your availability (prior to the end of this week):
2019 Nov 03
2
Full restrict support - status update
Hi Alexey,
Adding llvm-ir bitcode support means adding/adapting the tags for LOAD/STORE instructions and adding
the support for the noalias_sidechannel at the right places.
I had a short attempt to implement it when preparing the public patches, but I am not familiar with that
part of the llvm code. When I noticed that it would take a lot longer than anticipated, I postponed it.
Also because it
2019 May 20
3
GlobalISel: Very limited pattern matching?
Hi all,
I'm trying to get GlobalISel up and running on an off-tree
architecture and am thinking I must be doing something wrong, given by
how few things actually work.
Namely, any ImmLeaf pattern will fail to match if there is a
(TRUNC/ZEXT/SEXT) applied to the constant operand, all of which are
commonly created through Legalization. This is due to G_CONSTANT being
explicitly looked for by
2019 Oct 04
3
Full 'restrict' support in LLVM.
Hi all,
I am happy to announce that Synopsys wants to contribute its
implementation of 'C99 restrict' to the LLVM project. [1]
This implementation is based on Hal Finkel's local restrict patches
and on the 'RFC: Full 'restrict' support in LLVM' [2]
Any help with extra testing and code review is welcome.
To be generally useful, there are also some small gaps [1] that
2020 Jul 14
2
LLVM Alias Analysis Technical Call - New Doodle Poll
Hi, everyone,
A quick reminder: This call will start in approximately four hours. See below for how to join. On our current agenda:
Agenda
* Full restrict patch
* Observation and clarification
* Issues encountered
* Speed up in intersection code - O(nlog(n))
* Calling Verifier after LoopVectorize pass?
-Hal
Hal Finkel
Lead, Compiler Technology and Programming