similar to: [LLVMdev] -Os

On 07/23/2013 05:19 AM, Konstantin Tokarev wrote: > > 23.07.2013, 16:05, "reed kotler" <rkotler at mips.com>: >> When I use -Os with a clang that implicitly calls llc, I get much >> different code than when call clang first with -Os and then call llc. > clang does NOT call llc internally. I understand. It's invoking that functionality is what I meant to say

23.07.2013, 16:05, "reed kotler" <rkotler at mips.com>: > When I use -Os with a clang that implicitly calls llc, I get much > different code than when call clang first with -Os and then call llc. clang does NOT call llc internally. > How do I get these two paths to generate the same code? Call llc with -Os? -- Regards, Konstantin

On 02/23/2013 04:28 AM, David Chisnall wrote: > Hi Reed, > > -Os could do with some love. It is more or less the same set of passes as -O2, but with a few things that are most likely to increase code size removed. We have had problems with it in the past for FreeBSD's bootloader. By tweaking the set of default passes added for -Os, I got the size down by about 20%, but I didn't

We already divided out our classes as you did for ARM. The problem here is that we have a store/load byte/halfword to/from a Frame object. We know at that time that it's not going to be possible to store it using SP because there is only such instructions for store/load of a word. What we would want to do is to move SP into a Mips 16 register and then do a indexed load/store off of that

Mips 16 is basically to save space. I want to start comparing real benchmarks with llvm and gcc -mips16. Does -Os have any meaning currently to clang? llvm? What about inlining? Is inlining turned off? Tia. Reed

At one of the BOFS during the llvm conference a few years back, one of the Apple managers stated in effect that their view of -Os was to get some modest savings but only if performance has near 0 impact. On 02/23/2013 09:45 AM, Reed Kotler wrote: > On 02/23/2013 04:28 AM, David Chisnall wrote: >> Hi Reed, >> >> -Os could do with some love. It is more or less the same set

You are trying to do a few different things here, and a uniform solution may not work for all of them. For a fixed instruction sequence, e.g. a special kind of move-and-branch sequence used for tail calls, you probably want a pseudo. If you are trying to combine arbitrary instructions together, e.g. Thumb IT blocks, you probably want to use bundles, even if the sequences are a fixed length. I

On 02/25/2014 02:38 PM, Eric Christopher wrote: > On Tue, Feb 25, 2014 at 2:32 PM, reed kotler <rkotler at mips.com> wrote: >> On 02/25/2014 09:30 AM, Richard Sandiford wrote: >>> reed kotler <rkotler at mips.com> writes: >>>> On 02/24/2014 04:42 PM, Eric Christopher wrote: >>>>> On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at

AFAIK, You have two choices: use a pseudo that is lowered into separate instructions later as part of asm emission, or use MI bundles. The former is generally what existing targets use for this sort of thing, but perhaps the second would work better for you. Cameron On Feb 16, 2013, at 8:37 PM, Reed Kotler <rkotler at mips.com> wrote: > Some of my pseudos do conditional branch .+4 and

Ok. That's a somewhat different problem, then. Devil will be in the details of what you want to do. A few options. First is to always have a standard frame pointer register available and reference off of that. Caveat: dynamic stack realignment and vararrays muck with that more than a bit. Second is what gcc is doing and reserve a register just for this in addition to the frame register.

I see what my problem is here.... I'll continue to move further. Seems like Richards fix is still okay. On 02/25/2014 02:42 PM, Eric Christopher wrote: > On Tue, Feb 25, 2014 at 2:41 PM, reed kotler <rkotler at mips.com> wrote: >> On 02/25/2014 02:38 PM, Eric Christopher wrote: >>> On Tue, Feb 25, 2014 at 2:32 PM, reed kotler <rkotler at mips.com> wrote:

On 02/24/2014 04:42 PM, Eric Christopher wrote: > On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at mips.com> wrote: >> I need to leave soon and will take a look in the morning. >> >> I did look at the autoconf input files configure.ac >> >> There is a disable-zlib but not a disable-valgrind, even though it seems >> like there used to be.

Actually, SP is already not in the mips 16 register class but there is some C++ code that is common to mips32, mips64 and mips16 that is wanting to use SP. It's kind of awkward but does work except in this case of load/store haflword and byte to stack objects. Maybe I'm shooting myself in the foot there. I don't know that code too well so maybe I need to look into it. There are

In the following example with gcc style builtins, in once case llvm.powi.f64 is emitted and in the other just a call to library function powf. ~/llvm/build/Debug+Asserts/bin/clang -S -emit-llvm pow1.c Why is that? Is there a way to force the call to an llvm style builtin? Tia. Reed -------------- next part -------------- A non-text attachment was scrubbed... Name: pow1.c Type: text/x-csrc

One of my reasons for lowering things early is that I need to get an accurate count of the size of things. Some of the pseudos even have instructions like compare immediate, which in Mips 16 has two forms depending on the magnitude of the immediate field. Though I suppose it's possible to leave things as a pseudo and calculate their size, though I'm not sure where I could store the

On 06/04/2012 05:17 PM, Daniel Berlin wrote: > Can we get back to the substantive discussion about your ideas for > lessening the technical debt? The lessening requires enlisting people that are willing to do this as opposed to doing fun science like cool optimization. I,for example, find the documentaiton, cleanup and refactoring to be interesting so I don't feel cheated to work on

If you can't make an executable test from C or C++ code then how do you know something works. Just by examination of the .s? On 09/30/2014 03:18 PM, Reed Kotler wrote: > If I wanted to call this function that they generated by hand, from C or > C+ code, how would that be done? > > if have seen cases where a real boolean gets generated but it was > something fairly involved.

On 06/10/2014 05:51 PM, Pete Cooper wrote: > Hi Reed > > You can do this on the instruction itself by telling it 2 operands > must be the same register. For example, from X86: > > let Constraints = "$src1 = $dst" in > defm INSERTPS : SS41I_insertf32<0x21, "insertps">; > > Thanks, Hi Pete, Sorry. I should have been more specific. I'm

On 02/25/2014 09:30 AM, Richard Sandiford wrote: > reed kotler <rkotler at mips.com> writes: >> On 02/24/2014 04:42 PM, Eric Christopher wrote: >>> On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at mips.com> wrote: >>>> I need to leave soon and will take a look in the morning. >>>> >>>> I did look at the autoconf input files

FWIW, I'm putting together (hopefully to be done by the end of this weekend) a substantial refactoring of the TableGen backend API along with shiny new documentation (reStructuredText with sphinx) of all of TableGen, including documentation about how to write backends and---depending on how adventurous I get---a more detailed coverage of the syntax. Also, Reed, in your TableGen talk, IIRC,