similar to: [LLVMdev] Basic instructions for LLVM and Control Flow graph extraction

Displaying 20 results from an estimated 4000 matches similar to: "[LLVMdev] Basic instructions for LLVM and Control Flow graph extraction"

2013 Jul 09
0
[LLVMdev] Basic instructions for LLVM and Control Flow graph extraction
This isn't by itself too difficult, as I have done something similar recently, but does require some modifications of LLVM. The basic algorithm is simple: For each ISA instruction, create a new MachineInstr and add it to the current MachineBasicBlock. At each branch instruction, add it to the current MBB and add it to a list and create a new MBB. After creating your list of MBB, iterate
2017 Nov 11
2
Update control flow graph when splitting a machine basic block?
Thank you for your reply! > Every MachineBasicBlock has a list of successors; you can access it with > the successors() accessor. That's what you should be using for any CFG > analysis. I am aware of these methods of class MachineBasicBlock, which allows one to access a MachineBasicBlock's successors and predecessors in the CFG. But the CFG itself may no longer be valid if a
2011 Oct 18
3
[LLVMdev] Question regarding basic-block placement optimization
On Tue, Oct 18, 2011 at 2:59 PM, Cameron Zwarich <zwarich at apple.com> wrote: > On Oct 18, 2011, at 2:53 AM, Chandler Carruth wrote: > > > Hello, > > > > I'm working on basic-block placement optimizations based on branch > probability information. I've run into a stumbling block though. One of the > existing passes to do this, essentially a dead pass
2012 Jul 30
0
[LLVMdev] global control flow graph at machine code level
Hi Abhishek, On Sunday, July 29, 2012 18:32:11 AbhishekR wrote: > It seems like I may have to modify the way MachineFunction is instantiated in MachineFunctionAnalysis. Instead of doing it per Function, it may have to be done for the entire Module by instantiating MachineFunction objects for every Function inside the Module. This might require major changes to the PassManager framework as well.
2012 Jul 29
3
[LLVMdev] global control flow graph at machine code level
Hi all, I am trying to build a global control flow graph at machine code level. Essentially, I need the handles to the MachineFunction's corresponding to every call site inside a MachineFunction in order to get the handles to MachineBasicBlock's with return statements inside the callee. Currently, the codegen module processes one MachineFunction at a time and hence I can't find a way
2008 Sep 16
10
autospec is not picking latest changes
Hey Guys. I just updated a project form 1.1.4 that was working with autotest 3.10 without issues: 1) Updated spec/model/project_spec.rb and it fired only that spec. 2) Updated app/model/project.rb and it fired only the matching spec file. After the update of rspec and rspec-rails as plugins a few minutes ago, it only run the controller specs and no other. Also, it doesn''t matter which
2020 Nov 17
3
[RFC] Control Flow Sensitive AutoFDO (FS-AFDO)
Hi all, Here I include an RFC for control flow sensitive AutoFDO (FS-AFDO). This is a joint work with David Li. Questions and feedback are welcome. Thanks, Rong ============= [RFC] Control Flow Sensitive AutoFDO (FS-AFDO) 1. Motivation AFDO profile is derived from PMU samples from running an earlier build binary. PMU samples are indexed by the IP addresses. An offline tool uses the debug
2008 Apr 16
3
[LLVMdev] Possible bug in LiveIntervalAnalysis?
Hi, In the LiveIntervalAnalysis::runOnMachineFunction, there is a code to compute the MBB2IdxMap, by remembering for each MBB its start and end instruction numbers: unsigned MIIndex = 0; for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end(); MBB != E; ++MBB) { unsigned StartIdx = MIIndex; for (MachineBasicBlock::iterator I = MBB->begin(), E =
2007 Jun 22
4
[LLVMdev] df_ext_iterator in LiveIntervalAnalysis
I would like to make a suggestion. In the LiveIntervalAnalysis class, instead of numbering the instructions in the order in which basic blocks are stored in the machine function, use the df_ext_iterator. It will order the instruction according to the dominance tree (or it seems to be doing so). There are many advantages in doing this. One of them is that, once you traverse the dominance tree
2014 Dec 08
2
[LLVMdev] Virtual register problem in X86 backend
Hi, I'm having trouble using virtual register in the X86 backend. I implemented a new intrinsic and I use a custom inserter. The goal of the intrinsic is to set the content of the stack to zero at the end of each function. Here is my code: MachineBasicBlock * X86TargetLowering::EmitBURNSTACKWithCustomInserter( MachineInstr *MI, MachineBasicBlock
2010 Oct 20
1
[LLVMdev] MachineBasicBlock insertion
Hi all, I am really stumped on a problem for long. I could not figure out why. That is why i am here. OK, here is the problem: I tried to insert a MachineBasicBlock into a function. Here is the code snippet: // insert a machine basic block with the error_label into MF and before I // Pred is the predecessor of the block to be inserted // the new basic block is inserted right before I void
2017 Aug 22
5
[RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.
Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >> Hi, >> >> >>
2020 Mar 13
3
Why MachineBasicBlcok doesn't have transferPredecessors() ?
for example I want to insert a new machine bb “before” a specific machine bb. or split a mbb and keep the later one as the original one. (to keep the label/Blackadder's correct t) (or keep other property of mbb) so I need to transfer the original mbb's predecessor to the new mbb. Nicolai Hähnle <nhaehnle at gmail.com> 於 2020年3月13日 週五 23:57 寫道: > On Fri, Mar 13, 2020 at
2014 Oct 28
2
[LLVMdev] Problem in X86 backend (again)
Hi, I'm still having problems implementing my custom inserter in the X86 backend. I found a solution to my last problem (http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-October/078296.html), by using a virtual register. The binary works when it's compiled in -O0, but not in -O1,-O2,... I really can't figure what I'm doing wrong... Any idea? Here is the code of my custom
2008 Apr 16
0
[LLVMdev] Possible bug in LiveIntervalAnalysis?
Hi I'm seeing something probably related to this. I'm getting an assert from the lower_bound in LiveIntervals::findLiveinMBBs (from a checking std:: VS2005 implementation). Idx2MBBMap has two elements in it, both of which have a .first of 0. (I believe because of an empty MBB in the function below, so StartIndex doesn't advance). scott On Wed, Apr 16, 2008 at 2:52 AM, Roman
2008 Oct 10
5
Solution for autospec not working
Hello, I have noticed that, since version 1.1.4, autotest/autospec does not run any of my specs. After getting a hint from http://b.logi.cx/2008/10/9/non-auto-spec, I dove a bit deeper into the code and found that spec is no longer being run by ruby. I monkey-patched Autotest::Rspec in my .autotest file so that spec is again executed (using code taken from version 1.1.4). autospec is now
2020 Mar 13
2
How to simply split MachineBasicBlock ?
Hi I am developing some machine function pass. I want to split MachineBasicBlcok when I find some specific machine instruction. But I don't insert or delete any machine instruction. I just "simply" , "purely" split the MachineBasicBlcok. (So, I stole the idea from ARM64BranchRelaxation::splitBlockBeforeInstr.) This is my code : // I would pass call instruction to
2008 Apr 18
1
[LLVMdev] Possible bug in LiveIntervalAnalysis?
Can you file a bug so I don't forget? I'm a little occupied right now. But I'll take care of this soon. Evan On Apr 16, 2008, at 10:52 AM, Scott Graham wrote: > Hi > > I'm seeing something probably related to this. I'm getting an assert > from the lower_bound in LiveIntervals::findLiveinMBBs (from a checking > std:: VS2005 implementation). Idx2MBBMap has two
2014 Nov 06
2
[LLVMdev] Should the MachineVerifier accept a MBB with a single (landing pad) successor?
Hi all, I've been investigating a machine verifier failure on the attached testcase, and I'm tempted to say the verifier is wrong and should accept it. Skip the description for the proposed change. On AArch64, the verifier complains with: *** Bad machine code: MBB exits via unconditional branch but doesn't have exactly one CFG successor! *** - function: t4 - basic
2007 Jun 22
0
[LLVMdev] df_ext_iterator in LiveIntervalAnalysis
On Thu, 21 Jun 2007, Fernando Magno Quintao Pereira wrote: > I would like to make a suggestion. In the LiveIntervalAnalysis class, > instead of numbering the instructions in the order in which basic blocks > are stored in the machine function, use the df_ext_iterator. It will order > the instruction according to the dominance tree (or it seems to be doing > so). There are many