similar to: [LLVMdev] EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes are gone

Hi, I was comparing the way LLVM generates the exception table and it looks a bit different from what GCC (arm-none-eabi-g++) generates. Maybe that's because clang is not generating ARM IR when I do: $ clang -c -emit-llvm -march=arm -mcpu=cortex-a8 -mtriple=arm-none-eabi exception.cpp -o exception.clang.bc clang: warning: argument unused during compilation: '-mcpu=cortex-a8' clang:

My understanding is that with the new attribute system we should deprecate and eventually remove the codegen command line options. On 17 May 2013 06:04, reed kotler <rkotler at mips.com> wrote: > I can't say this is a bug it is changed behavior from before the new > attribute scheme. > > This issue may appear with other attributes. (there are other attributes > that clang

I can't say this is a bug it is changed behavior from before the new attribute scheme. This issue may appear with other attributes. (there are other attributes that clang will now place on each function) If you run clang as a single pass to create a .ll and don't say -msoft-float, it puts the attribute use-soft-float=false on every function. (It used to be that in that case

On 05/17/2013 08:08 PM, Rafael Espíndola wrote: > My understanding is that with the new attribute system we should > deprecate and eventually remove the codegen command line options. How is that possible? > On 17 May 2013 06:04, reed kotler <rkotler at mips.com> wrote: >> I can't say this is a bug it is changed behavior from before the new >> attribute scheme.

MachineRegisterInfo is maintaining a list of live-out registers for the MachineFunction. It contains the return value registers, and is typically created by XXXISelLowering::LowerReturn(). Various passes after instruction selection need to look at this list to determine which physical registers are live in return blocks. Eventually, the register allocators copy these live-out registers onto the

I'm trying to 'lower' an operation that needs to create a node in the SD that is an intrinsic call.... what is the best way to do this? I see in the DAGBuilder it calls 'setValue' which adds to the map NodeMap[V] where V is the key and the passed in SDValue is the value but I'm not sure this is a good way to do it since these are local to SelectionDAGBuilder and the

On Nov 24, 2007, at 7:28 PM, Sanjiv Gupta wrote: > Could anybody guide me what information do I need to know about my > target in order to provide the target lowering info to the llvm DAG > generator? We do not have any fixed registers for argument passing. > Everything including the formal and actual arguments will take part in > a global interprocedural regalloc. You don't

thanks Evan, I have just started writing td files. Any ideas how do I describe instructions for an accumulator based machine. The other pecularity is that we do not want to have any software stack. So the instructions like load and store have no meanings. In that case, how do I lower instructions that operate on stack frame? TIA, Sanjiv On 11/26/07, Evan Cheng <evan.cheng at apple.com>

On Thu, Mar 5, 2015 at 4:19 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Thanks for the reply: > > So should LLVM continue to assume 8-bit byte addressing? It would be nice, > not only to us but potential future machines, to have a permanent fix to > this assumption? This sounds reasonable yes? > > Marking them as Custom in XXXISelLowering still produces error, the

Matt, Thanks for the response. Is there an example in the code somewhere of doing the intrinsic ID method? I don't need to put it a lot of places so I'm not sure it warrants adding a node. Thanks. On Tue, Feb 2, 2016 at 12:35 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Feb 2, 2016, at 09:29, Ryan Taylor via llvm-dev < > llvm-dev at lists.llvm.org>

I'm trying to replace SDIvRem (whch returns two i16 types) with a custom that returns i32 or i16. I am getting the Assertion (!Node || ResNo < Node->getNumValues() && "Invalid result number for the given node!") Seems that it doesn't like returning one value but how do you return more than one value? I am doing this in the LowerOperation for the case SDIVREM and a

We've got both an sqrtf and an expf opcode in our architecture. If I call sqrt() on the C side, I see the sqrtf opcode show up in the generated assembly. However, if I call exp() on the C side, I don't see the expf opcode show up on the generated assembly, I see a call to an exp function from libm. Here's what we've got in our TargetInstrinfo.td file for both of these

Hi Mats, It's private backend. I will try describing what I am dealing with. struct S { unsigned int a : 8; unsigned int b : 8; unsigned int c : 8; unsigned int d : 8; unsigned int e; } We want to read S->b for example. The size of struct S is 64 bits, and seems LLVM treats it as i64. Below is the IR corresponding to S->b, IIRC. %0 = load

Hi, there I am writing an backend, and I met a problem. We don't have load/store instructions for vector predicate registers(vpr for short). The hardware has 64 vector registers(vr for short) and 8 vector predicate registers. And there is no move instructions between vr and vpr. vr supports many operations, and vpr supports vpror, vprxor, vprand and vprinv operations. A vr has 512 bits, and

Note: Question is written after describing what I have coded. Hello LLVMDevs, I am trying to impliment floating point comparsion for an architecture which supports following type of floating point comparision if FPU is available: fcmp.un --> true if one of the operand is NaN fcmp.lt --> ordered less than, if any input NaN then return false fcmp.eq --> ordered equal, if any input NaN

On Nov 21, 2010, at 7:10 PM, Wesley Peck wrote: > Attached is a patch that renames ISD::BIT_CONVERT to ISD::BITCAST as per http://www.llvm.org/OpenProjects.html, #3 under Code Generator Improvements. I have not updated the OpenProjects.html file itself as I could not find that file in the source code. > > The patch itself also includes elimination of whitespace at the end of lines

Attached is a patch that renames ISD::BIT_CONVERT to ISD::BITCAST as per http://www.llvm.org/OpenProjects.html, #3 under Code Generator Improvements. I have not updated the OpenProjects.html file itself as I could not find that file in the source code. The patch itself also includes elimination of whitespace at the end of lines because my VIM settings do that automatically. If this is not desired

LLVM appears to support Library functions for ISD::SRA ,ISD::SHL, and ISD::SRL, as they are properly defined in RuntimeLibCalls.def. The library functions defined in RuntimeLibCalls.def (among others) are these: HANDLE_LIBCALL(SRA_I16, "__ashrhi3") HANDLE_LIBCALL(SRA_I32, "__ashrsi3") HANDLE_LIBCALL(SRA_I64, "__ashrdi3") However, setting

On Thu, Mar 9, 2017 at 9:35 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > On 02/25/2017 03:06 AM, vivek pandya via llvm-dev wrote: > > Note: Question is written after describing what I have coded. > > Hello LLVMDevs, > > I am trying to impliment floating point comparsion for an architecture > which > supports following type of floating point comparision if FPU

I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation on the 2 8-bit subregs of that 16-bit register. That means the only practical solution for 32-bit shifts is to lower to a libcall but my situation for 16-bit shifts sounds similar to yours for 32-bit shifts. I