Displaying 8 results from an estimated 8 matches similar to: "[LLVMdev] Question regarding the x86 SBB instruction."
2013 Jun 28
0
[LLVMdev] Question regarding the x86 SBB instruction.
Look at the __builtin_addc* builtins in clang. I am currently working on an optimization which transforms said intrinsics into chains of ADCs/SBBs.
Michael
On Jun 28, 2013, at 5:51 AM, James Courtier-Dutton <james.dutton at gmail.com> wrote:
> Hi,
>
> I have the x86 SBB instruction. how should I represent this in LLVM
> IR. (as part of a decompiler from binary to LLVM IR)
2013 Mar 12
0
[LLVMdev] help decompiling x86 ASM to LLVM IR
On 3/12/2013 11:20 AM, James Courtier-Dutton wrote:
> It compiles with GCC -O2 to (rather cleverly removing any branches):
> 0000000000000000 <test61>:
> 0: 83 ff 01 cmp $0x1,%edi
> 3: 19 c0 sbb %eax,%eax
> 5: 83 e0 df and $0xffffffdf,%eax
> 8: 83 c0 61 add $0x61,%eax
>
2020 Mar 12
4
Correct modelling of instructions with types smaller than the register class
Hi Quentin,
thank you for the reply! I have a couple more questions that came up
when I tried to implement this today. I hope you can help me out with
this again!
Am 09.03.20 um 23:31 schrieb Quentin Colombet:
> I would expect that you could create a register class and register
> bank for the special register. That way you have something to map to
> when you do register bank select.
2020 Mar 02
2
Correct modelling of instructions with types smaller than the register class
Hi Quentin,
thank you for the reply! This clears up a lot of the questions I was
having. It seems like we should definitely invest some time in rewriting
some of our legalization rules then! I also posted some questions
further down below. I would appreciate getting your opinion on them.
> Hi Dominik,
>
> I’ll do a brief reply here and if you want more information we can talk further
2013 Mar 12
6
[LLVMdev] help decompiling x86 ASM to LLVM IR
Hi,
I am looking to decompile x86 ASM to LLVM IR.
The original C is this:
int test61 ( unsigned value ) {
int ret;
if (value < 1)
ret = 0x40;
else
ret = 0x61;
return ret;
}
It compiles with GCC -O2 to (rather cleverly removing any branches):
0000000000000000 <test61>:
0: 83 ff 01 cmp $0x1,%edi
3:
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 5:26 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
>> Can you explain why you chose the approach of using a new pass?
>> I pictured removing LegalizeDAG's type legalization code would
>> mostly consist of finding all the places that use TLI.getTypeAction