similar to: [LLVMdev] Length restriction in tablegen

On Jun 25, 2013, at 1:45 AM, Anitha B Gollamudi <anitha.boyapati at gmail.com> wrote: > Is there some sort of restriction over class length names in td files. Only your own sanity, as far as I know. > For e.g. something like below gives an abort with tablegen. The abort goes away when I reduce the name "my_target_intrinsics_class..." to something shorter. I have not

I'm still slightly confused. Is the error now fixed or is there still a bug in LLVM's integrated assembler? On Mon, Mar 11, 2013 at 4:49 AM, Anitha B Gollamudi < anitha.boyapati at gmail.com> wrote: > On 11 March 2013 17:00, Duncan Sands <baldrick at free.fr> wrote: > > Hi Anitha, > > > > > >> Ah, I am taking back my above words w.r.t encoding.

On 11 March 2013 10:06, Anitha B Gollamudi <anitha.boyapati at gmail.com> wrote: > On 23 January 2013 00:20, Craig Topper <craig.topper at gmail.com> wrote: >> >> Are you still having issues with FMA4? I wonder if PR15040 is related. A >> fix was just committed. Unfortunately r173176 does not fix this. I have updated the trunk and ran...Miscompare still persists.

Looks like recent changes to Attributes.h broke the dragonegg build. I am building with latest clang and llvm trunk. clang version 3.2 (trunk 165928) (llvm/trunk 165925) Target: x86_64-unknown-linux-gnu Thread model: posix >>>>> Compiling TypeConversion.cpp /local/home/anitha/dragonegg/src/TypeConversion.cpp: In function âllvm::FunctionType* ConvertArgListToFnType(tree,

Can you send the binaries compiled with and without the integrated assembler. Maybe I can figure out the encoding problem. I've been unsuccessful figuring it out myself so far. On Tue, Mar 12, 2013 at 12:34 AM, Anitha B Gollamudi < anitha.boyapati at gmail.com> wrote: > On 12 March 2013 09:51, Craig Topper <craig.topper at gmail.com> wrote: > > I'm still slightly

Hi Duncan I am facing a build error about __builtin_iceil when compiled with dragonegg using -ffast-math option. My dragonegg is built with gcc-4.7.0 (I am compiling namd spec benchmark here again). Any idea? g++ -march=bdver2 -save-temps -fplugin=/home/anboyapa/install/bin/dragonegg.so -O2 -march=bdver2 -save-temps -fplugin=/home/anboyapa/install/bin/dragonegg.so -mno-fma -mfma4 -ffast-math

On 12 March 2013 09:51, Craig Topper <craig.topper at gmail.com> wrote: > I'm still slightly confused. Is the error now fixed or is there still a bug > in LLVM's integrated assembler? > The error is not fixed yet (even with fix mentioned in PR15040 http://llvm.org/bugs/show_bug.cgi?id=15040#c4) With the updated trunk, clang still gives an error when FMA4 is enabled but

Hi Anitha, Thanks for your answer but -mcpu=cortex-a9 -mattr=+vfp4 doesn' t enable fused mac generation for me. I would like just to understand why -mtriple=armv7-eabi enables it while -mcpu=cortex-a9 seems to disable it ? Seb > -----Original Message----- > From: Anitha Boyapati [mailto:anitha.boyapati at gmail.com] > Sent: Thursday, November 08, 2012 10:22 AM > To: Sebastien

Hi, Is there any existing support/on going work for zeroing buffers in llvm infrastructure? (either in the form of intrinsics or IR code buffer erasure?) My basic "grep" did not show up any. Please let me know any info on this. I will be glad to hear out! -- Anitha

On 23 January 2013 00:20, Craig Topper <craig.topper at gmail.com> wrote: > > Are you still having issues with FMA4? I wonder if PR15040 is related. A > fix was just committed. It seems to be so! I will look into it immediately. Apologies for the late e-mail. I ran out of time devoted for this PR and moved on. Coincidentally, only today I came back to this PR for further

Are you still having issues with FMA4? I wonder if PR15040 is related. A fix was just committed. On Wed, Nov 7, 2012 at 3:22 AM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: > > > On 7 November 2012 15:29, Duncan Sands <baldrick at free.fr> wrote: > >> >> That way the output should be exactly the same as the output dragonegg >> would >>

Hi Bastien, Weird gcc is generating fma for my platform STEricsson Novathor with Linaro, code works. It also works when I use LLVM to generate fma (using llc -mtriple=armv7-eabi). Maybe someone from ARM can answer the question ? Seb From: JF Bastien [mailto:jfb at google.com] Sent: Friday, November 09, 2012 5:36 PM To: Sebastien DELDON-GNB Cc: Anitha Boyapati; llvmdev at cs.uiuc.edu Subject:

On 7 April 2013 14:54, Sam Parker <S.Parker3 at lboro.ac.uk> wrote: > Hi Anitha, > > memri is just describing that the address contains two components, an > immediate and a register, and how to handle them in the instruction printer. > The STWU expects a memri operand, and that is what is passed from the Pat. > My confusion is how operands of STWU from "Pat

On 5 November 2012 14:32, Duncan Sands <baldrick at free.fr> wrote: > Hi Anitha, > > > http://llvm.org/bugs/show_bug.**cgi?id=14185<http://llvm.org/bugs/show_bug.cgi?id=14185> >> I am stuck on analysis. Does any one have alternate suggestions on >> debugging >> llvm? (Please refer to comments for the work done so far) >> > > try to reduce a

Hi, How do "Pat" operands get matched? I am trying to follow the example given in http://llvm.org/docs/CodeGenerator.html#selectiondag-process In the latest trunk of ppcintrinfo.td following pattern is defined: def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), (STWU $rS, iaddroff:$ptroff, $ptrreg)>; I understand that input operand list i.e. ins of

Hi Anitha, > Ah, I am taking back my above words w.r.t encoding. -no-integrated-as > does fix the issue! This definitely points towards FMA4 encoding in > clang's integrated assembler. This fits into the analysis as well - > dragonegg *might not* be using integrated assembler at all. you are right, dragonegg does not use the integrated assembler. Ciao, Duncan.

Hello All... I have installed xen 3.3. I m running a Virtual Machine using an image file that has fedora 8 installed in it. When i view the Virtual Machine using VNC Viewer or on the browser using tight vnc,there appears 2 pointers .I need to solve this problem. Kindly suggecst me the correct solution. Waiting for responses. -- Thanks and Regards Anitha

Hi, I have a simple question w.r.t the order of operands used in dag pattern matching in target files. Some of them seem intuitive. But I want to get it clarified anyway. I am using a pattern from X86InstrFMA.td in the below example. Consider FMA3 pattern (simplified). let Constraints = "$src1 = $dst" in { multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand

Hi, A question from r162999 changes: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?r1=162999&r2=162998&pathrev=162999 For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and "MemOp4" like those of "rm" or "rr" ? multiclass fma4s< > ... def mr : FMA4<opc, MRMSrcMem, (outs

On 6 November 2012 14:52, Duncan Sands <baldrick at free.fr> wrote: > Hi Anitha, > > > On 06/11/12 10:19, Anitha Boyapati wrote: > >> Hi Duncan >> I am facing a build error about __builtin_iceil >> > > it's surely just that dragonegg doesn't have any support for this builtin. > ok. Just verified that Target.cpp and x86_builtins do not have