similar to: [LLVMdev] tablegen question

Hi Micah, On Tue, Jun 25, 2013 at 03:47:14PM +0000, Micah Villmow wrote: > How do you specify in a tablegen pattern that all destination registers are also source registers? I know I could just duplicate them, but I was wondering if there was a way it could be done without doing this. Basically an inplace operation. > I'm not sure if there is a good way to do this. The

Hi all, Muppet from the UK asking for help We are just about to have a T1 line installed in our office in Dallas and "Advantex" the supplier has sent a questionnaire asking a number of questions. I have put the question area at the bottom of the email, we will be using Digium's hardware. could anybody help :-) In the UK when I asked for a E1, number of trunks required and the

Hey All, I'm just daydreaming here.. but what's the status of SIP-T in Asterisk? I haven't been able to find a whole lot of info on SIP-T but seems like just an extension of SIP. Right? Now if I had a PSTN Gateway (that is a SS7 gateway) that supported SIP-T, could I signal * with SIP-T from it and have asterisk utilize MGCP to sieze a particular DS0 on a remote DS1? Hmm.. What am

I am trying to make an in/out trunk group comprised of 4 DS0's using E&M Wink signalling. The first four channels of a DS1 on a T100P are being used for the group. Outbound calls work fine, but inbound calls fail. The other 20 DS0 channels are used for a PRI. Does the configuration shown below look okay? I've tried setting 'immediate => yes' without success, but it

hi, i have some newbie questions about channel banks. i have an adtran act-1241 sitting around. it accepts D4 modules, and it contains a number of e&m cards. first of all, how does this thing work? a t1 contains 24 channels, and i noticed that the channel bank has space for 24 cards. what do these cards do? what are their outputs? the ones that are in there have some outputs on the front

That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: multiclass instmcRegImm<...> { def rr: inst<...>; def ri: inst<...>; def ir: inst<...>; def ii: inst<...>; } multiclass instmc<...> { defm i8 : instmcRegImm<...>; ^-- repeat for 15

All, I need to run this by everyone and see if someone has any idea's. I have a asterisk server setup and currently am receiving the inbound calling number where the name should be. My setup is.... One pri terminating into a Cisco 2431 router Sip messages from the Cisco get sent to a asterisk server linksys ata's a each remote end. I can receive the calling name if the call originates

Possible to add a test case? Micah > -----Original Message----- > From: Sebastian Pop [mailto:spop at codeaurora.org] > Sent: Wednesday, June 20, 2012 1:40 PM > To: Villmow, Micah > Cc: llvmdev at cs.uiuc.edu; llvm-commits at cs.uiuc.edu > Subject: Re: [LLVMdev] How to define macros in a tablegen file? > > On Wed, Jun 20, 2012 at 12:34 PM, Sebastian Pop <spop at

On Wed, Jun 20, 2012 at 3:40 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Possible to add a test case? I am not really sure what I would check. At first, I thought to add a testcase to test/TableGen; as this patch does not modify tablegen, it doesn't make sense. What kind of test should I write for this? The test should be a tablegen file that includes

Eli, Thanks for the tips. I've been able to get something working using a custom instruction inserter, however, I'm still having the problem of linking together the setcc and the select_cc commands. I want to turn the setcc into a comparison and use the results in the select_cc register. However, the comparison information is in the select_cc instruction and the result of the comparison

I'm trying to find examples of the foreach pattern being used in tablegen files. The problem I am trying to solve is to simplify the amount of tablegen code I have to produce because each operand of an instruction can be a register or a literal. So for binary, we have 4 instructions, ternary, 8, and quaternary 16 combinations. Instead of writing all the combinations out, I'd like to use

I believe multiclasses can be nested. Could that help you reduce the duplication? --Sean Silva On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: > > multiclass

I'm not at the machine that has the changes, but it was failing at index 0. Micah From: Owen Anderson [mailto:resistor at mac.com] Sent: Thursday, April 19, 2012 3:35 PM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output

Right, it's failing when it tries to materialize a move of a constant into a register. But it's only trying to do that because it previously failed to fold the constant into the AND. What you need to do is step through the path it takes when matching the AND node, and try to figure out why it ends up selecting the register-register version rather than the register-immediate version.

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Jakob Stoklund Olesen > Sent: Friday, August 03, 2012 10:02 AM > To: Sebastian Pop > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] TableGen related question for the Hexagon > backend > > > On Aug 2, 2012, at 11:24 PM, Sebastian Pop

Hello, I urgently need a histogram of the vector geo1$ds1 but: > hist(geo1$ds1) Error in hist(geo1$ds1) : unused argument(s) ( ...) I can use density, summary, boxplot and stem with this vector but not hist ? Any suggestions ? Thanks in advance, Detlef Groth > density(geo1$ds1) Call: density(x = geo1$ds1) Data: geo1$ds1 (1412 obs.); Bandwidth 'bw' = 0.2805

Hello R users, When trying to fit a nonlinear mixed model to a respiration time series, I get the following error message: Error in recalc.varFunc(object[[i]], conLin) : dims [product 30] do not match the length of object [34] In addition: Warning message: In conLin$Xy * varWeights(object) : longer object length is not a multiple of shorter object length Below is an example that generates

I think a multiclass may be a better fit for what you are trying to do. In fact, this is the canonical example for multiclasses: <http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-and-instances>. --Sean Silva On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I’m trying to find examples of the foreach pattern being used in

With my backend code gen I want to assign calling parameters to a list of registers, but since I'm targeting a virtual instruction set. I don't want to be limited by the number of registers. Is there a way using TableGen to specify just a starting register to assign to for the CallingConv class and then have it just use sequential registers? Micah Villmow Systems Engineer Advanced

I am attempting to lower the selectCC instruction to the instruction set of the backend I'm working on and I cannot seem to find a way to correctly implement this instruction. I know how this instruction should get implemented; I just have yet to find a way to do it. I want the select_cc instruction to be lowered into a comparison followed by a conditional move. I've attempted to use a