similar to: [LLVMdev] Telling clang/LLVM a data object is "near"

also in /etc/sysctl.d/ On Thu, Dec 24, 2015 at 8:58 AM, Gordon Messmer <gordon.messmer at gmail.com> wrote: > On 12/23/2015 05:08 AM, Ofer Hasson wrote: > >> By running "systemctl status systemd-sysctl" I also receive the same >> output, but a simple "cat /proc/sys/vm/swappiness" returns the default >> value, and not the one set by my conf file.

You are correct, I'll refine my problem, By running "systemctl status systemd-sysctl" I also receive the same output, but a simple "cat /proc/sys/vm/swappiness" returns the default value, and not the one set by my conf file. But, if I run "/usr/lib/systemd/systemd-sysctl" the "cat /proc/sys/vm/swappiness" does return the correct value. Any idea ? Does

On 12/23/2015 11:12 PM, Ofer Hasson wrote: > [root at web-devel-local-1 ~]# /usr/lib/systemd/systemd-sysctl > [root at web-devel-local-1 ~]# cat /proc/sys/vm/swappiness > 10 So... you know that it works when you run it from a root shell, but not during boot. Is the file labeled properly? Anything in audit.log?

----- Mail original ----- > De: "Ofer Hasson" <hassonofer at gmail.com> > ?: "centos" <centos at centos.org> > Envoy?: Jeudi 24 D?cembre 2015 11:36:00 > Objet: Re: [CentOS] systemd-sysctl not running on boot > [root at web-devel-local-1 ~]# ll -Z /etc/ | grep sysctl > drwxr-xr-x. root root system_u:object_r:etc_t:s0 sysctl.d > >

Hey all, After upgrading to CentOS 7.2, non of my servers run systemd-sysctl on boot. So far, I tried running manually /usr/lib/systemd/systemd-sysctl, it runs smoothly and updates all the parameters. I also ran sysctl --system, which also executes successfully. I checked within systemd, and systemd-sysctl is wanted by the sysinit.target which is wanted by the multi-user.target - the one I boot

This patch introduces an optimized assembler version of md5_process(), the inner loop of MD5 checksumming. It affects the performance of all MD5 operations in rsync - including block matching and whole-file checksums. Performance gain is 5-10% depending on the specific CPU. Originally created by Marc Bevand and placed in the public domain, later integrated into OpenSSL. This is the original

Hallo, I am using rsync to copy remote files into a local directory. I use the following flags: "--remove-sent-files --partial-dir=/tmp --partial --temp-dir=/tmp --backup --suffix=.bak". I need the partial issue since in the final destination I must have only closed and full files. I need to remove the sent files from the destination since I need to avoid transferring the same file

Hello everyone, In the file *lib/CodeGen/AsmPrinter/AsmPrinter.cpp*, I would like to obtain an MCInst corresponding to its MachineInstr. Can anyone tell me a way to do that? If that is not possible, then, I would like to know if a given MachineInstr is an *lea *instruction and I would like to know if the symbol involved with this lea instruction is a jump-table. For instance, given a

Was there any development on this? I noticed that clang still produces a lea for the testcase in llvm.org/pr13320. On 28 September 2012 11:36, Nowicki, Tyler <tyler.nowicki at intel.com> wrote: > Hi, > > > > Here is an update on our proposal to improve the uses of LEA on Atom > processors. > > > > 1. Disable current generation of LEAs > > > > Due to

So here is quick patch solving the problem, now it should be PIC. -- Miroslav Lichvar lichvarm@phoenix.inf.upol.cz -------------- next part -------------- --- lpc_asm.nasm.orig Wed Jul 18 02:23:40 2001 +++ lpc_asm.nasm Sat Nov 17 21:09:46 2001 @@ -59,10 +59,10 @@ ; ALIGN 16 cident FLAC__lpc_compute_autocorrelation_asm_ia32 - ;[esp + 24] == autoc[] - ;[esp + 20] == lag - ;[esp + 16] ==

Good morning in the Lord Regarding the port of libtheora1.1beta3 for OpenBSD for amd64 and the problem I described at: http://lists.xiph.org/pipermail/theora/2009-August/002640.html Attached is a patch for libtheora/patches/patch-lib_x86_mmxencfrag_c I can play videos with it. ?Does it work for you? Best regards -- Dios, gracias por tu amor infinito.

On Oct 2, 2013, at 11:48 PM, Evan Cheng <evan.cheng at apple.com> wrote: > The two address pass is only concerned about register pressure. It sounds like it should be taught about profitability. In cases where profitability can only be determined with something machinetracemetric then it probably should live it to more sophisticated pass like regalloc. > > In this case, we

I've got a question about instruction selection for a backend I'm writing. The target has two register classes, RC1 and RC2. The instruction set is far from orthogonal. The ADD instruction is two address with both register/immediate and register/memory forms. The register operand is in the RC1 class. The LEA instruction is three address with the destination register in the RC2 class.

I am new to Asterisk and VoIP. I have been given the task of setting up a telephone network in US and India. When customers call the US location, the calls should route to India (using VoIP) and handle there. The Indian location should be able to call Us numbers using the Voip to save money. The solution should be flexible enough to support initial of 5 simultaneous calls with the option to

Hi, We are getting ready to implement several heuristics for correctly using LEAs to avoid stalls in the address generator on Atom. Our plan is to: 1. Disabling LEA generation on Atom in X86ISelDAGToDAG:: SelectLEAAddr() for all but a few pseudo-instructions 2. Identify loads and stores in a X86PassConfig::addPreEmitPass() pass and examine several preceding instructions to

Hi, Here is an update on our proposal to improve the uses of LEA on Atom processors. 1. Disable current generation of LEAs Due to a 3 cycle stall between the ALU and the AGU any address generation done using math instruction will cause a stall on loads and stores which are within 3 cycles of the address generation. Consequently, the heuristics for using LEAs efficiently must know how many

I submitted the problem report to clang's bugzilla but no one seems to care so I have to send it to the mailing list. clang 3.7 svn (trunk 229055 as the time I was to report this problem) generates slower code than 3.5 (Apple LLVM version 6.0 (clang-600.0.56) (based on LLVM 3.5svn)) for the following code. It is a "8 queens puzzle" solver written as an educational example. As

The regressions in the performance of generated code, introduced by the llvm 3.6 release, don't seem to be limited to this 8 queens puzzle" solver test case. See... http://www.phoronix.com/scan.php?page=article&item=llvm-clang-3.5-3.6-rc1&num=1 where a bit hit in the performance of the Sparse Matrix Multiply test of the SciMark v2.0 benchmark was observed as well as others.

Actually there is no miscompile there as esi isn't needed. The flags are which the cmove is using. 342: shr esi,0x5 345: lea rbp,[rip+0x0] # 34c <llvm::sys::getHostCPUName()+0xbc> 34c: lea r12,[rip+0x0] # 353 <llvm::sys::getHostCPUName()+0xc3> 353: cmove rbp,r12 <- this is dependent on the flags from the shift. I think your real problem is

Hi all. I'm looking for an advice on how to deal with inefficient code generation for Intel Nehalem/Westmere architecture on 64-bit platform for the attached test.cpp (LLVM IR is in test.cpp.ll). The inner loop has 11 iterations and eventually unrolled. Test.lea.s is the assembly code of the outer loop. It simply has 11 loads, 11 FP add, 11 FP mull, 1 FP store and lea+mov for index