Displaying 20 results from an estimated 3000 matches similar to: "[LLVMdev] Error in the example of sext instruction in reference manual"
2013 Jun 21
0
[LLVMdev] Error in the example of sext instruction in reference manual
On Jun 20, 2013, at 4:39 PM, Bin Tzeng <bintzeng at gmail.com> wrote:
> Hi all,
>
> There might be a simple error in the LLVM reference manual. The example for sext instruction:
>
> %X = sext i8 -1 to i16 ; yields i16 :65535
>
> %X should yield i16: -1, as opposed to 65535.
> Here is the simple patch (also attached):
These are the same value.
-Chris
>
2013 Jun 21
2
[LLVMdev] Error in the example of sext instruction in reference manual
Thanks for the reply. Just for a little more clarity, is i16, i32...
signed, unsigned, or just a bit pattern?
On Thu, Jun 20, 2013 at 9:17 PM, Chris Lattner <clattner at apple.com> wrote:
>
> On Jun 20, 2013, at 4:39 PM, Bin Tzeng <bintzeng at gmail.com> wrote:
>
> > Hi all,
> >
> > There might be a simple error in the LLVM reference manual. The example
2013 Jun 21
0
[LLVMdev] Error in the example of sext instruction in reference manual
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Bin Tzeng
> Subject: Re: [LLVMdev] Error in the example of sext instruction in reference manual
> Just for a little more clarity, is i16, i32... signed, unsigned, or
> just a bit pattern?
It's just a bit pattern. The operations performed on it can treat it as signed, unsigned, or
2013 Nov 13
3
[LLVMdev] dominator, post-dominator and memory leak
Hi Henrique,
Thanks for the quick reply!
On Tue, Nov 12, 2013 at 9:13 PM, Henrique Santos <
henrique.nazare.santos at gmail.com> wrote:
> PRE normally uses a latest placement algorithm to do something of the sort.
> I don't know about GVN/PRE, but older version of PRE might have it.
> Just placing the calls to free at the predecessors (dominated by BB12) of
> the dominance
2013 Nov 15
2
[LLVMdev] dominator, post-dominator and memory leak
Hi Henrique,
I have tried using -mergereturn and inserting a free into the predecessors
of dominance frontier of malloc block and it caused double free. It is
possible for multiple free's to be inserted on the path from malloc to an
exit. For example, in the following CFG:
BB10 (malloc)
/ \
BB11 BB12
... / \ / \
2013 Nov 13
0
[LLVMdev] dominator, post-dominator and memory leak
>
> It seems that placing the calls to free at the predecessors of dominance
> frontier is inadequate. It is possible that there are exit blocks that are
> dominated by BB12 (calls to malloc). I guess we can also insert calls to
> free at these exit blocks too.
That crossed my mind a few minutes later. : )
If you're interested, PRE.cpp existed last at r25315. It calculates the
2013 Nov 13
2
[LLVMdev] dominator, post-dominator and memory leak
Thanks! I will try that and see whether it works.
On Wed, Nov 13, 2013 at 5:01 AM, Henrique Santos <
henrique.nazare.santos at gmail.com> wrote:
> It seems that placing the calls to free at the predecessors of dominance
>> frontier is inadequate. It is possible that there are exit blocks that are
>> dominated by BB12 (calls to malloc). I guess we can also insert calls to
2013 Nov 15
0
[LLVMdev] dominator, post-dominator and memory leak
Try breaking the critical edges (-break-crit-edges).
This way, a new block will be created between BB13 and BB11 (call this
BB11.break) and BB15 and BB12 (call this BB12.break).
The predecessors of the dominance frontier will, thus, be BB11.break,
BB12.break, and BB14.
When we enter through a block with a call to malloc(), we will end up in
one of the blocks in the dominance frontier (kind of).
2013 Nov 13
0
[LLVMdev] dominator, post-dominator and memory leak
Bill,
Just in case this is relevant for you: If you're working with C++ code, or otherwise have any functions that might throw exceptions, you might also need to catch those exceptions in order to free the allocated memory. This will involve looking for calls to functions that mayThrow(), changing their calls to invokes, and freeing the memory before resuming the unwinding.
-Hal
-----
2008 Oct 06
3
[LLVMdev] sext..to instruction
Hi,
I have a question about the "sext..to" instruction. In the document, I found
two examples:
%x = sext i8 -1 to i16
It means:
i8 -1 = 1111 1111 --> 1111 1111 1111 1111 = i16
how can it determinate, that the i16 value %x positive is (65535)?
And the second example:
%y = sext i1 true to i32
1 --> 1111 1111 1111 1111 1111 1111 1111 1111
In this example, %y is -1
I'm not sure
2013 Jul 30
3
[LLVMdev] Disable memset synthesization
Hi all,
LLVM is smart that it can synthesize llvm.memset, llvm.memcpy etc. from
loops, which can be lowered into calls to memset, memcpy and so on. Is
there an option that can disable this optimization? For some cases, I do
not want the code to depend on libc.
Thanks in advance!
Bin
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2013 Nov 13
2
[LLVMdev] dominator, post-dominator and memory leak
Hi all,
I have been writing a pass to heapify some alloca's (it is
pessimistization, not optimization). For example, in the following control
flow graph, there is a call to malloc inserted in block BB12. In order to
avoid memory leak, free's are needed. The free cannot be inserted in BB23
because BB23 is not dominated by BB12. There are two ways to go I can think
of here. One way is to
2008 Oct 06
0
[LLVMdev] sext..to instruction
> I'm not sure about it, when sext to results a positve/negative value?
sext does signed-extension, zext does unsigned-extension.
This means that zext always extends by zero bits,
while with sext the additional bits are all copies of the
top bit of the original value. So with sext, if it was
negative in the original type when considered as a signed
value, then it will be negative in the
2015 Apr 29
2
[LLVMdev] [LoopVectorizer] Missed vectorization opportunities caused by sext/zext operations
Hi,
This is somewhat similar to the previous thread regarding missed vectorization
opportunities (http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-April/084765.html),
but maybe different enough to require a new thread.
I'm seeing some missed vectorization opportunities in the loop vectorizer because SCEV
is not able to fold sext/zext expressions into recurrence expressions (AddRecExpr).
This
2019 Sep 27
2
Shift-by-signext - sext is bad for analysis - ignore it's use count?
In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext
is simply a shift-by-zext. But the transform is limited to single-use sext.
We can quite trivially get a case where there are two shifts by the same sext:
https://godbolt.org/z/j6mO3t <- We should handle those cases.
In https://reviews.llvm.org/D68103#1686130 Sanjay Patel notes that this
sext is intrusive for
2013 Aug 07
1
[LLVMdev] DataFlowSanitizer design discussion
15.06.2013, 00:53, "Bin Tzeng" <bintzeng at gmail.com>:
> It is interesting. I can see some use cases with such a tool. To me, source-level implementation
> is not as accurate as binary translation. For instance, it is hard to check the taint for return addresses
> since there is no concept of return instructions on source level.
Well, on many architectures there is no
2015 May 06
2
[LLVMdev] [LoopVectorizer] Missed vectorization opportunities caused by sext/zext operations
For
void test0(unsigned short a, unsigned short * in, unsigned short * out) {
for (unsigned short w = 1; w < a - 1; w++) //this will never overflow
out[w] = in[w+7] * 2;
}
I think it will be sufficient to add a couple of new cases to
ScalarEvolution::HowManyLessThans --
zext(A) ult zext(B) == A ult B
sext(A) slt sext(B) == A slt B
Currently it bails out if it sees a non-add
2010 Jul 13
1
[LLVMdev] The question of sext instruction implementation
I saw the description in llvm documenattion for sext is as the following :
-- sext (CST to TYPE)
Sign extend a constant to another type. The bit size of CST must
be smaller or equal to the bit size of TYPE. Both types must be
integers.
But in the code of llvm-2.6, the judge condition just allow smaller to
the bit size of TYPE as the following :
case Instruction::SExt:
return
2019 Oct 01
2
Shift-by-signext - sext is bad for analysis - ignore it's use count?
Thanks for taking a look!
On Tue, Oct 1, 2019 at 9:09 PM Philip Reames <listmail at philipreames.com> wrote:
> On 9/27/19 1:40 PM, Roman Lebedev via llvm-dev wrote:
> > In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext
> > is simply a shift-by-zext.
>
> Just to make sure I'm following, the reasoning here is that the shift
> amount must
2012 Jan 16
1
[LLVMdev] PTX backend fails instruction selection for load of sext
Loads (on ptx64) with an sext of a computed index operand fail instruction selection:
LLVM ERROR: Cannot select: 0x7ff01401c210: i64,ch = load 0x10580e820, 0x7ff01401b510, 0x7ff01401b910<LD4[%memref1], sext from i32> [ID=8]
0x7ff01401b510: i64 = PTXISD::LOAD_PARAM 0x10580e820, 0x7ff01401b410 [ORD=2] [ID=6]
0x7ff01401b910: i64 = undef [ORD=4] [ID=3]
This is for code of the form:
%ptr