Displaying 20 results from an estimated 3000 matches similar to: "[LLVMdev] Vector type LOAD/STORE with post-increment."
2013 Jun 19
0
[LLVMdev] Vector type LOAD/STORE with post-increment.
On 19 June 2013 11:32, Francois Pichet <pichet2000 at gmail.com> wrote:
> I am talking about something like this:
> vldr d16, [sp, #8]
>
Hi Francois,
This is just using the offset, not updating the register (see ARM ARM
A8.5). Post-increment only has meaning if you write-back the new value to
the register like:
vldr d16, [sp], #8
Did you mean write-back? or just
2012 Sep 05
3
[LLVMdev] Unaligned vector memory access for ARM/NEON.
Hello Jim,
Thank you for the response. I may be confused about the alignment rules
here.
I had been looking at the ARM RVCT Assembler Guide, which seems to
indicate vld1.16 operates on 16-bit aligned data, unless I am
misinterpreting their table
(Table 5-11 in ARM DUI 0204H, pg 5-70,5-71).
Prior to the table, It does mention the accesses need to be "element"
aligned, where I took
2012 Sep 05
0
[LLVMdev] Unaligned vector memory access for ARM/NEON.
Hmmm. Well, it's entirely possible that it's LLVM that's confused about the alignment requirements here. :)
I think I see, in general, where. I twiddled the IR to give it higher alignment (16 bytes) and get:
extend: @ @extend
@ BB#0:
vldr d16, [r0]
vmovl.s16 q8, d16
vstmia r1, {d16, d17}
vldr d16, [r0, #8]
add r0, r1, #16
vmovl.s16 q8, d16
vstmia
2012 Sep 06
2
[LLVMdev] Unaligned vector memory access for ARM/NEON.
Hello,
Thanks again. We did try overestimating the alignment, and saw the vldr
you reference here.
It looks like a recent change (r161962?) did enable vld1 generation for
this case (great!) on darwin, but not linux.
I'm not sure if the effect of lowering load <4 x i16>* align 2 to
vld1.16 this was intentional in this change or not.
If so, my question is what is the preferable way to
2012 Sep 06
1
[LLVMdev] Unaligned vector memory access for ARM/NEON.
On Sep 5, 2012, at 4:58 PM, Jim Grosbach <grosbach at apple.com> wrote:
> Hmmm. Well, it's entirely possible that it's LLVM that's confused about the alignment requirements here. :)
>
> I think I see, in general, where. I twiddled the IR to give it higher alignment (16 bytes) and get:
> extend: @ @extend
> @ BB#0:
> vldr d16,
2012 Sep 06
2
[LLVMdev] Unaligned vector memory access for ARM/NEON.
On Sep 6, 2012, at 2:48 PM, David Peixotto <dpeixott at codeaurora.org> wrote:
> Hi Pete,
>
> We ran into the same issue with generating vector loads/stores for vectors
> with less than word alignment. It seems we took a similar approach to
> solving the problem by modifying the logic in allowsUnalignedMemoryAccesses.
>
> As you and Jim mentioned, it looks like the
2012 Sep 06
0
[LLVMdev] Unaligned vector memory access for ARM/NEON.
Hi Pete,
We ran into the same issue with generating vector loads/stores for vectors
with less than word alignment. It seems we took a similar approach to
solving the problem by modifying the logic in allowsUnalignedMemoryAccesses.
As you and Jim mentioned, it looks like the vld1/vst1 instructions should
support element aligned access for any armv7 implementation (I'm looking at
Table A3-1
2012 Sep 06
0
[LLVMdev] Unaligned vector memory access for ARM/NEON.
-----Original Message-----
From: Bob Wilson [mailto:bob.wilson at apple.com]
Sent: Thursday, September 06, 2012 3:39 PM
To: David Peixotto
Cc: 'Peter Couperus'; 'Jim Grosbach'; 'Jakob Olesen'; llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Unaligned vector memory access for ARM/NEON.
On Sep 6, 2012, at 2:48 PM, David Peixotto <dpeixott at codeaurora.org> wrote:
2012 Sep 07
2
[LLVMdev] Unaligned vector memory access for ARM/NEON.
On Sep 6, 2012, at 4:40 PM, David Peixotto <dpeixott at codeaurora.org> wrote:
> -----Original Message-----
> From: Bob Wilson [mailto:bob.wilson at apple.com]
> Sent: Thursday, September 06, 2012 3:39 PM
> To: David Peixotto
> Cc: 'Peter Couperus'; 'Jim Grosbach'; 'Jakob Olesen'; llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Unaligned vector
2012 Jul 05
2
[LLVMdev] RE : Vector argument passing abi for ARM ?
Hi Duncan,
I also thought it was a bug, especially since it worked with LLVM 3.0, but since it is not defined by ABI, I was not sure if I need to submit it as a BUG.
I wanted to be sure that it is an actual BUG before submitting it and got the not-a-bug answer.
Here is a small example to reproduce the problem I'm experiencing:
; ModuleID = 'bugparam.ll'
target datalayout =
2013 Oct 21
1
[LLVMdev] MI scheduler produce badly code with inline function
Hi Andy, I'm working on defining new machine model for my target,
But I don't understand how to define the in-order machine (reservation
tables) in new model.
For example, if target has IF ID EX WB stages
should I do:
let BufferSize=0 in {
def IF: ProcResource<1>; def ID: ProcResource<1>;
def EX: ProcResource<1>; def WB: ProcResource<1>;
}
def :
2016 May 11
3
[LLVMdev] Improving the quality of debug locations / DbgValueHistoryCalculator
The most obvious place where it is lacking at the moment is that it only supports DBG_VALUEs in registers. Adding support for constant values, memory locations, and fp constants would be a big win!
thanks,
Adrian
> On May 11, 2016, at 2:52 PM, Francois Pichet <pichet2000 at gmail.com> wrote:
>
> In retrospect I totally agree with you. I am looking at LiveDebugValue again to see
2012 Jul 05
0
[LLVMdev] RE : Vector argument passing abi for ARM ?
Hi Sebastien,
> I also thought it was a bug, especially since it worked with LLVM 3.0, but since it is not defined by ABI, I was not sure if I need to submit it as a BUG.
yes it is a bug.
> I wanted to be sure that it is an actual BUG before submitting it and got the not-a-bug answer.
I didn't read Nadav's reply as saying there was no bug, in fact he explicitly
said in his email
2013 Oct 15
0
[LLVMdev] MI scheduler produce badly code with inline function
On Oct 14, 2013, at 3:27 AM, Zakk <zakk0610 at gmail.com> wrote:
> Hi all,
> I meet this problem when compiling the TREAM benchmark (http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched
>
> The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code.
A bug for this is welcome. Pretty soon, I’ll
2016 May 12
2
[LLVMdev] Improving the quality of debug locations / DbgValueHistoryCalculator
> On May 12, 2016, at 11:00 AM, Francois Pichet <pichet2000 at gmail.com> wrote:
>
> Here is a specific case that make the debugging experiences degraded on my target:
> This is a loop simplified CFG:
>
> BB#0:
> %R5<def> = OR_rr %R0, %R49 // this is %R5 only def.
> DBG_VALUE %R5, %noreg, !"argc", <!18>; line no:4
> Successors
2012 Jul 05
0
[LLVMdev] Vector argument passing abi for ARM ?
Hi Sebastien,
> Thanks for the quick answer, how do I know which type is legal/illegal with respect to calling convention ?
the code generators are supposed to produce working code no matter what the
parameter type is. The fact that the ARM ABI doesn't specify how <2 x i8>
is passed just means that the code generators can pass it using whatever
technique it feels like (since it
2013 Nov 21
2
[LLVMdev] Unaligned load/store for callee-saved 128-bit registers
----- Original Message -----
> From: "Francois Pichet" <pichet2000 at gmail.com>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "Chad Rosier" <mcrosier at codeaurora.org>, "Jakob Stoklund Olesen" <jolesen at apple.com>, "LLVM Developers Mailing
> List" <llvmdev at cs.uiuc.edu>
> Sent: Thursday, November
2016 May 11
2
[LLVMdev] Improving the quality of debug locations / DbgValueHistoryCalculator
> On May 11, 2016, at 2:09 PM, Francois Pichet <pichet2000 at gmail.com> wrote:
>
> Good point.
>
> Currently yes a DEBUG_VALUE "x", vreg0 will be added in BB2. Now I realize this might be wrong in some (corner?) cases where vreg0 no longer refer to "x"
>
> My fix would be to propagate the DEBUG_VALUE only if "x" is associated with only a
2013 Oct 14
2
[LLVMdev] MI scheduler produce badly code with inline function
Hi all,
I meet this problem when compiling the TREAM benchmark (
http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched
The small function will be scheduled as good code, but if opt inline this
function, the inline part will be scheduled as bad code.
so I rewrite a simple code as attached link (foo.c), and compiled with two
different methods:
*method A:*
*$clang -O3 foo.c -static -S
2013 Jul 21
2
[LLVMdev] Disable vectorization for unaligned data
Ok any quick workaround to limit vectorization to 16-byte aligned 128-bit
data then?
All the memory copying done by ExpandUnalignedStore/ExpandUnalignedLoad is
just too expensive.
On Sat, Jul 20, 2013 at 12:52 PM, Arnold Schwaighofer <
aschwaighofer at apple.com> wrote:
>
> On Jul 19, 2013, at 3:14 PM, Francois Pichet <pichet2000 at gmail.com> wrote:
>
> >
> >