similar to: [LLVMdev] ARM struct byval size > 64 triggers failure

Displaying 20 results from an estimated 7000 matches similar to: "[LLVMdev] ARM struct byval size > 64 triggers failure"

2013 Jun 19
2
[LLVMdev] ARM struct byval size > 64 triggers failure
I missed that the testing case is returning a struct. You are right in VARegSaveSize. For callee: sub sp, sp, #16 push {r11, lr} mov r11, sp sub sp, sp, #8 str r3, [r11, #20] str r2, [r11, #16] str r1, [r11, #12] ldr r1, [r11, #76] The beginning of the input struct @ sp_at_entry - 16 - 8 + 12 = sp_at_entry -12 # of leftover bytes 67-12 = 55 r11+76 is @ sp_at_entry - 24 + 76 = sp_at_entry
2013 Jun 20
0
[LLVMdev] ARM struct byval size > 64 triggers failure
On 20 June 2013 13:35, Rajesh Viswabramana <rajesh.vis at samsung.com> wrote: > - What considerations will be made from llvm side to make abi > compatibile with gcc/other compilers for arm - struct byval size >64 bytes. > Hi Rajesh, I'm not sure I follow your question, but in general, the idea is to be compatible with ABIs, not with specific compilers. So, if compiler X
2013 Jun 18
0
[LLVMdev] ARM struct byval size > 64 triggers failure
Hi Rajesh, The callee code looks okay to me > Assembly for check114 > --------------------------------------------------------------- > sub sp, sp, #16 > push {r11, lr} > mov r11, sp > sub sp, sp, #8 > str r3, [r11, #20] > str r2, [r11, #16] > str r1, [r11, #12] > ldr r1,
2013 Jun 20
1
[LLVMdev] ARM struct byval size > 64 triggers failure
> - "since ABI says the stack pointer needs to be 8 byte aligned at function entry point" (taken from Manman's reply) > What will be considered as entry point here? > Is it place of SP Adjustments "sub sp, sp, #16" > (Or) Is it place of first user instruction(end of prologue) "ldr r2, .LCPI0_0" Eight byte stack alignment is a
2013 Jun 18
3
[LLVMdev] ARM struct byval size > 64 triggers failure
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2013 Jun 18
0
[LLVMdev] ARM struct byval size > 64 triggers failure
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2013 Feb 08
2
[LLVMdev] JIT on armhf
On 08/02/13 14:42, Renato Golin wrote: [...] > Can you paste the result of a "clang -v -mcpu=CPU file.c" on your box? I > want to see what are the arguments and the assembler/linker it's > choosing to use. What CPU are we talking about? The box itself is an Allwinner A10; armv7l. /proc/cpuinfo says it's got swp half thumb fastmult vfp edsp neon vfpv3. I've been
2012 Jul 18
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
On Wed, Jul 18, 2012 at 4:31 PM, Renato Golin <rengolin at systemcall.org> wrote: > On 18 July 2012 15:24, salvatore benedetto > <salvatore.benedetto at gmail.com> wrote: >> I'm not sure how to interpret the above output, but I don't understand >> why if say -triple armv4t-none--gnueabi . > > Ok, we're getting there... ;) Glad you are confident.
2012 Aug 29
0
[LLVMdev] Is cross-compiling for ARM on x86 with llvm/Clang possible?
Hi Journeyer First, thank you so much for your updates on your experiments. I am currently following your steps but have found myself stuck with the following error: /usr/lib/gcc/arm-linux-gnueabi/4.6/../../../../arm-linux-gnueabi/bin/ld: this linker was not configured to use sysroots clang: error: linker command failed with exit code 1 (use -v to see invocation) I used the command string you
2012 Nov 22
0
[LLVMdev] Extended Inline asm with double data type crashes clang
Hi all, I tried same code on gcc for arm(hard float), double f2 () { double x = 10.0; asm ("" : "=r" (x) : "0" (x)); return x; } > arm-linux-gnueabi-gcc -S -mhard-float pr39058.c -O2 Generates proper code, mov r3, #0 mov r2, #0 movt r3, 16420 fmdrr d0, r2, r3 bx lr But llvm crashes, If data type is "double",
2012 Jun 20
3
[LLVMdev] Is cross-compiling for ARM on x86 with llvm/Clang possible?
Hello, Thank you for your kind attention to my issue and your help. I changed the tool chain and tried again. And there is a little progress but still have some problem. Using --sysroot doesn't make clang use linker(ld) in the cross tool. Most important question is how I can make clang use cross tool linker. Let me show you my experiment and questions below. There are two questions. [Run]
2012 Nov 21
2
[LLVMdev] Extended Inline asm with double data type crashes clang
Thanks Rafael, Hello All, Could anyone please comment, which part in selectiondag need to be understood/modified to fix this. Regards, Rajesh On Wed, Nov 21, 2012 at 2:38 AM, Rafael EspĂ­ndola < rafael.espindola at gmail.com> wrote: > I reported http://llvm.org/pr14393 to track it. > > On 20 November 2012 05:18, rajesh viswabramana > <viswabramana.rajesh at
2012 Nov 20
0
[LLVMdev] Extended Inline asm with double data type crashes clang
I reported http://llvm.org/pr14393 to track it. On 20 November 2012 05:18, rajesh viswabramana <viswabramana.rajesh at gmail.com> wrote: > Hi, > > Clang crashes when below snippet of code is compiled (used latest svn > version) > > double func1() > { > double x ; > asm ( "" : "=r"(x) : "0"(x) ); > return x; > } >
2012 Dec 28
0
[LLVMdev] Function inline causes crash in clang for .ast to .s
Hi, Could anyone please comment on this ? Regards, Rajesh On Wed, Dec 19, 2012 at 6:54 PM, rajesh viswabramana < viswabramana.rajesh at gmail.com> wrote: > Hi, > > Clang crashes when tried to compile from .ast to .s for below sample code, > > inline-test.c > ** > *extern inline int func1 (void) { return 0; } > inline int func1 (void) { return 1; }* > >
2013 Jun 19
0
[LLVMdev] ARM struct byval size > 64 triggers failure
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2013 Jun 20
0
[LLVMdev] Fwd: Re: Re: ARM struct byval size > 64 triggers failure
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2013 Jun 21
0
[LLVMdev] ARM struct byval size > 64 triggers failure
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2012 Jul 18
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
On Wed, Jul 18, 2012 at 4:15 PM, Renato Golin <rengolin at systemcall.org> wrote: > On 18 July 2012 14:57, salvatore benedetto > <salvatore.benedetto at gmail.com> wrote: >> $ clang -march=armv7-m -mfloat-abi=soft -ccc-host-triple >> armv7m-none-gnueabi testReference.cpp -c >> fatal error: error in backend: CPU: 'cortex-m3' does not support ARM >>
2010 Jan 10
1
[LLVMdev] building a llvm-arm-elf crosscompiler on OSX 10.5
Dear ML, Anton, Thank you for your answer and your help. I had a look at ARM.td of LLVM 2.6 (in lib/Target/ARM..) where I found following definitions: // V4T Processors. def : ProcNoItin<"arm7tdmi", [ArchV4T]>; def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>; def : ProcNoItin<"arm710t", [ArchV4T]>; def :
2018 Mar 15
0
[RFC] Stop giving a default CPU to the LTO plugin?
On 3/15/2018 9:43 AM, Peter Smith via llvm-dev wrote: > Hello everyone, this is most likely Arm specific, but could affect > other targets where there is a somewhat complex relationship between > the triple and mcpu option. > > At present when clang is used as a linker driver for the gold-plugin > and when using and an explicit -mcpu is not given to clang, then clang > will