similar to: [LLVMdev] TableGen lookup table recipe?

Displaying 20 results from an estimated 300 matches similar to: "[LLVMdev] TableGen lookup table recipe?"

2008 Jun 23
3
One-to-one matching?
Hi folks, Can anyone suggest an efficient way to do "matching without replacement", or "one-to-one matching"? pmatch() doesn't quite provide what I need... For example, lookupTable <- c("a","b","c","d","e","f") matchSample <- c("a","a","b","d") ##Normal match()
2013 May 31
2
[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)
I think the last time I pulled from trunk was probably end of last year. Some time ago. Does your reply intimate it's fixed on trunk? That would be great. (I don't sync too often to avoid churn with my TD.) Joe On Fri, May 31, 2013 at 4:21 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On May 31, 2013, at 4:07 PM, Joe Matarazzo <joe.matarazzo at gmail.com>
2013 May 31
2
[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)
The register coalescer treats virtual super register classes -- a sequential register range composed of multiple hardware registers -- as a register with sub registers. When making coalescing decisions it thinks that the virtual super reg interferes with sub reg instances, even though in reality they shouldn't conflict. That is, they are individual registers and would be better compared as
2013 Jan 31
2
[LLVMdev] Tablegen problem populating TSFlags
Jakob, I think this exactly what's happening. I debugged the resolveReferences for the ADD down into the resolve of TSFlags. It calls VarInit::getFieldInit for the "Val" field of "foo". The code is: Init *VarInit::getFieldInit(Record &R, const RecordVal *RV, const std::string &FieldName) const { if (isa<RecordRecTy>(getType()))
2013 Jun 01
0
[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)
On May 31, 2013, at 4:59 PM, Joe Matarazzo <joe.matarazzo at gmail.com> wrote: > I think the last time I pulled from trunk was probably end of last year. Some time ago. Does your reply intimate it's fixed on trunk? Yes, it’s been fixed recently. /jakob
2013 May 31
0
[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)
On May 31, 2013, at 4:07 PM, Joe Matarazzo <joe.matarazzo at gmail.com> wrote: > The register coalescer treats virtual super register classes -- a sequential register range composed of multiple hardware registers -- as a register with sub registers. When making coalescing decisions it thinks that the virtual super reg interferes with sub reg instances, even though in reality they
2009 Oct 05
3
how to have 'match' ignore no-matches
Hi all, I think this is a very basic question, but I'm new to this so please bear with me. I'm using match to translate elements of a data frame using a lookup table. If the content of a particular cell is not found in the lookup table, the function returns NA. I'm wondering how I can just ignore those cells, and return the original contents if no match is found in the lookup table.
2013 Jun 19
1
[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)
Was it the subreg lane masks / mapping that was added to address the missed coalescing? This solution is nice, but I don't think it'll work for me. I have 8-element vector registers that can be grouped into virtual super regs for bulk save/restore, and as soon as I have more than 4 in a tuple, the unsigned int used to hold the lane masks overflows and switches over to the "bit 31 set
2012 Mar 08
1
[LLVMdev] Register coalescing
Need some guidance about the right way to model this -- how would you model a backend with a handful of read-only physical registers that are passed as arguments to a function? I was emitting copyFromReg nodes in the LowerFormalArgument() routine, but then the register allocator and coalescer are resisting coalescing the COPY MI's for various reasons - for example, the read-only register class
2013 Feb 02
2
[LLVMdev] OperandWithDefaultOps question
Is it possible to use this operand class in an instruction that has a pattern defined? If so, can you write it with anything besides a ComplexPattern in the instruction's pattern DAG, to set it to a value? Can you refer to it at all? Or would it be added to the MachineInstr with the default value such that you could modify it later in the backend? If there is a non-ComplexPattern way to write
2012 Feb 10
1
[LLVMdev] Prevent DAG combiner from changing "store ConstFP, addr" to integer store
This code lives in DAGCombiner.cpp: ------------- // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { // NOTE: If the original store is volatile, this transform must not increase // the number of stores. For example, on x86-32 an f64 can be stored in one // processor operation but
2013 Jun 07
1
[LLVMdev] tablegen foreach question
What's the best (most concise) way to create the following four defs? D0 = (0, "A") D1 = (1, "B") D2 = (2, "C") D3 = (3, "D") I tried to use list of strings and the foreach construct, but apparently tablegen doesn't allow using identifiers to access array elements. $ cat tbl3.td def StrList { list<string> ls = ["A",
2001 Mar 10
0
Vorbis beta4 and -b256 mode quality
Hi. Since I'm interested in quality, I did some listening tests using Vorbis beta4, mode -b256. I think that ~256kbps, ~5.5:1 compression is still a good tradeoff because I can put 6-7 albums on 1 CD-R (assuming that the average length of an album is ~50 minutes) while retaining excellent quality. My comments: 1.) most songs are transparent but there are still some glitches that appear
2013 Feb 02
0
[LLVMdev] OperandWithDefaultOps question
On Fri, Feb 01, 2013 at 04:58:29PM -0800, Joe Matarazzo wrote: > Is it possible to use this operand class in an instruction that has a > pattern defined? If so, can you write it with anything besides a > ComplexPattern in the instruction's pattern DAG, to set it to a value? > Can you refer to it at all? Or would it be added to the MachineInstr > with the default value such that
2012 May 11
2
[LLVMdev] TableGen pattern for negated operand
I've been unable to come up with the TableGen recipe to match a negated operand. My target asm syntax allows the following transform: FNEG r8, r5 MUL r6, r8, r9 to MUL r6, -r5, r9 Is there a Pattern<> syntax that would allow matching *any* opcode (or even some subset), not just MUL, with a FNEG'd operand? I expect I can define a PatFrag: def fneg_su : PatFrag<(ops
2008 Jul 29
0
handling multiple lookup tables in rails
I''ve got an application that will have a handful of lookup tables. To be clear by this I mean tables that only have two attributes, id, name and are used to provide drop-down lists for other tables/forms so that these fields have "standard" values. I need 5 to 10 of these tables. I''m a ruby/rails neophyte but I''ve read Agile Web Devel with Rails, Rails
2015 Sep 18
2
GlobalOPT and sections
Hello everyone, This is a rather ancient code with Chris's name all over it, so I naturally feel humbled :) I see a conceptual issue in lib/Transforms/IPO/GlobalOpt.cpp with several optimizations that create a copy of GlobalVariable without copying attributes from the original one. Consider this one: http://llvm.org/doxygen/GlobalOpt_8cpp_source.html static bool
2018 Jul 05
0
write.table with quote=TRUE fails on nested data.frames
Looks like I?m bumping a lot into unexpected behaviour lately, but I think I found a bug again, but don?t have access to Bugzilla: Write.table (from core-package utils) doesn?t handle nested data.frames well, the quote arguments only marks top-level character (or-factor columns) for quoting, so this fails: df <- data.frame(a='One;Two;Three',
2011 Nov 09
1
[LLVMdev] AsmPrinter vs. MCAsmStreamer
I'm writing a backend using a mid-October svn snapshot of LLVM. I'm having a hard time figuring out the relationship between my XXXAsmPrinter and MCAsmStreamer. Can someone explain what each is responsible for? Looking at the existing targets, the XXXAsmPrinter implementations seem to implement both the legacy "create a .s file" behavior, using printInstruction/printOperand/etc
2012 May 11
0
[LLVMdev] TableGen pattern for negated operand
Hi Joe, Le 11/05/2012 02:13, Joe Matarazzo a écrit : > I've been unable to come up with the TableGen recipe to match a > negated operand. My target asm syntax allows the following transform: > > FNEG r8, r5 > MUL r6, r8, r9 > > to > > MUL r6, -r5, r9 > > Is there a Pattern<> syntax that would allow matching *any* opcode (or > even some