similar to: [LLVMdev] Register coalescer and reg_sequence (virtual super-regs)

On May 31, 2013, at 4:07 PM, Joe Matarazzo <joe.matarazzo at gmail.com> wrote: > The register coalescer treats virtual super register classes -- a sequential register range composed of multiple hardware registers -- as a register with sub registers. When making coalescing decisions it thinks that the virtual super reg interferes with sub reg instances, even though in reality they

I think the last time I pulled from trunk was probably end of last year. Some time ago. Does your reply intimate it's fixed on trunk? That would be great. (I don't sync too often to avoid churn with my TD.) Joe On Fri, May 31, 2013 at 4:21 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On May 31, 2013, at 4:07 PM, Joe Matarazzo <joe.matarazzo at gmail.com>

On May 31, 2013, at 4:59 PM, Joe Matarazzo <joe.matarazzo at gmail.com> wrote: > I think the last time I pulled from trunk was probably end of last year. Some time ago. Does your reply intimate it's fixed on trunk? Yes, it’s been fixed recently. /jakob

Was it the subreg lane masks / mapping that was added to address the missed coalescing? This solution is nice, but I don't think it'll work for me. I have 8-element vector registers that can be grouped into virtual super regs for bulk save/restore, and as soon as I have more than 4 in a tuple, the unsigned int used to hold the lane masks overflows and switches over to the "bit 31 set

Hello. Does anybody have an idea why I'm getting the error below when using llc with arguments -O1 -disable-cgp? Note that this error is not given when using llc -O0. (I'd like to mention also I'm using custom Instruction selection for BUILD_VECTOR, which gets converted in my back end's machine instrution VLOAD_D, although the custom code seems to always select

Hi Quentin, On 08/15/14 19:01, Quentin Colombet wrote: [...] >> The question is: How should true subregister definitions be >> expressed so that they do not interfere with each other? See the >> detailed problem description below. > > We do have a limitation in our current liveness tracking for > sub-register. Therefore, I am not sure that is possible. > >

Hello, I have a minimal testcase which crashes RegisterCoalescer in my out-of-tree target. It only crashes in Debug builds of llc---not in Release builds. Also, interesting to note that the x86 backend lowers this same testcase successfully. I did a quick search of bugs.llvm.org and found no matches. This implies that the problem is in my backend and/or how my backend interacts with

Hi all, Can someone please explain me how to use REG_SEQUENCE in tablegen? The arch i'm writing backend for has 32-bit regs, and it has a couple of 64-bit load/store instructions which use two neighboring regs at once, which i'm trying to employ using virtual regs with subs. For example, it I want to move one 64-bit virtual reg to another, I'm trying to use the following pattern:

Hi, Recently on trunk, the ovlaps list for a register got a dual entry on my target, which caused the RA to crash. Reg Subreg1 Subreg b Subreg2 Subreg b I have a register with two subregs that have subreg b in common. This causes the SuperReg to appear twice in the ovelaps list for Subreg b. As this causes a register allocator to crasch (it evicts a register, and then inremenets

Jakob, I think this exactly what's happening. I debugged the resolveReferences for the ADD down into the resolve of TSFlags. It calls VarInit::getFieldInit for the "Val" field of "foo". The code is: Init *VarInit::getFieldInit(Record &R, const RecordVal *RV, const std::string &FieldName) const { if (isa<RecordRecTy>(getType()))

Need some guidance about the right way to model this -- how would you model a backend with a handful of read-only physical registers that are passed as arguments to a function? I was emitting copyFromReg nodes in the LowerFormalArgument() routine, but then the register allocator and coalescer are resisting coalescing the COPY MI's for various reasons - for example, the read-only register class

Is it possible to define lookup tables as a list in tablegen, to map one value to another? Here's the template I was working on: ========================================= class LookupTable { list<int> mapping = [0, 8, 16, 24, 32]; } def LUT : LookupTable; class MyRegister<name, index> : Register<name> { let HWEncoding = LUT.mapping[index]; int otherVal = index;

Is it possible to use this operand class in an instruction that has a pattern defined? If so, can you write it with anything besides a ComplexPattern in the instruction's pattern DAG, to set it to a value? Can you refer to it at all? Or would it be added to the MachineInstr with the default value such that you could modify it later in the backend? If there is a non-ComplexPattern way to write

On May 11, 2012, at 6:35 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: > Hi, > > Recently on trunk, the ovlaps list for a register got a dual entry on my target, which caused the RA to crash. > > Reg > Subreg1 > Subreg b > Subreg2 > Subreg b > > I have a register with two subregs that have subreg b in common. This causes the

Hi I'm currently running asterisk with an fxo X100P and aTDM one port card in a small not world connected subnet, I've sucessfully setup two sip phone and one analog extension everything works fine with the analog phone but when you talk to someone on the sip phone the person at the sip phone can be heard with inteference. I've looked aroud the archives and found nothing specific.

Hi, I have a problem regarding sub-register definitions and LiveIntervals on our target. When a subregister is defined, other parts of the register are always left untouched - they are neither read or def:ed. It however seems that Codegen treats subregister definitions as somehow clobbering the whole register. The SSA-code looks like this after isel: (Reg0 and Reg1 are 16bit registers. Reg2,

This code lives in DAGCombiner.cpp: ------------- // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { // NOTE: If the original store is volatile, this transform must not increase // the number of stores. For example, on x86-32 an f64 can be stored in one // processor operation but

On Fri, Feb 01, 2013 at 04:58:29PM -0800, Joe Matarazzo wrote: > Is it possible to use this operand class in an instruction that has a > pattern defined? If so, can you write it with anything besides a > ComplexPattern in the instruction's pattern DAG, to set it to a value? > Can you refer to it at all? Or would it be added to the MachineInstr > with the default value such that

I've been unable to come up with the TableGen recipe to match a negated operand. My target asm syntax allows the following transform: FNEG r8, r5 MUL r6, r8, r9 to MUL r6, -r5, r9 Is there a Pattern<> syntax that would allow matching *any* opcode (or even some subset), not just MUL, with a FNEG'd operand? I expect I can define a PatFrag: def fneg_su : PatFrag<(ops

I want to full understand register coalescing and how to coalesce copies. From what I have seen from "SimpleRegisterCoalescing," "RegAllocLinearSpan," and "RegAllocPBQP" there are three indicators for the copy instruction x = copy y. Assume that the value number of x does not equal the value number of y. For "x = copy y", let the boolean values a,b, and c,